Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1997-02-28
1998-03-10
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
257204, 257211, 257365, 257401, H01L 2710
Patent
active
057264589
ABSTRACT:
An improved transistor design and methods of construction and testing for same. The novel transistor design method includes the steps of providing a transistor with multiple common gate areas; connecting each gate area to a pad; and adjusting the ratio of the area of the pad to the total of the gate areas to provide a predetermined ratio. The ratio may be adjusted by adjusting the size of the gate, in a single gate implementation, or adjusting the number of gates in a multiple gate configuration. The novel transistor includes a substrate, at least one source disposed on the substrate; at least one drain disposed on the substrate; and at least one gate disposed on the substrate between the source and the drain. The gate has a first layer of at least partially conductive material of area A.sub.g connected to a pad of area A.sub.p. In accordance with the present teachings, the antenna ratio R of the area of the pad A.sub.p to the area of the gate A.sub.g is a predetermined number. In practice, the ratio R would be chosen to be a minimum so that deleterious plasma currents attracted to the gate area would be reduced. In a particular implementation, the transistor includes plural gates each having a layer of at least partially conductive material of area A.sub.gn where n is any integer between 1 and N and where N is the total number of gates. In this case, the plural gates are interconnected and the ratio R is a predetermined number equal to A.sub.p /A.sub.gtotal, where A.sub.gtotal is the sum of the areas A.sub.gn and n is any integer between 1 and N. The novel method for testing multiple gate transistors includes the steps of connecting a first terminal of each of said transistors to a ground; interconnecting a second terminal of each transistor and applying a first source of supply potential; and selectively applying a second source of supply potential to a third terminal of a selected transistor.
REFERENCES:
patent: 3652906 (1972-03-01), Christensen
patent: 4631571 (1986-12-01), Tsubokura
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 5350710 (1994-09-01), Hong et al.
Advanced Micro Devices , Inc.
Mintel William
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