Hot carrier effect simulation for integrated circuits

Details Hot carrier effect simulation for integrated circuits Hot carrier effect simulation for integrated circuits

1998-05-29

2001-08-21

Choi, Kyle J. (Department: 2163)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C703S014000, C714S025000, C714S047300

Reexamination Certificate

active

06278964

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit simulation, and more specifically, to simulating hot carrier effects for integrated circuits.
BACKGROUND OF THE INVENTION
Designing integrated circuits (ICs) has become more complex and time consuming as improvements in semiconductor fabrication technology allow millions of transistors to be formed on a single substrate. Given the extraordinary increase in the complexity of contemporary ICs and the pressure to quickly develop improved designs, designers increasingly rely upon various computer-aided design (CAD) tools to design ICs. Design improvements are often achieved by conducting trial and error testing of many possible design solutions and selecting the “best” design solution. Thus, IC CAD tools allow a designer to more quickly determine a “best” design foranlC.
Most IC CAD tools can be generally categorized as either layout tools or design tools. Layout tools help a designer to create an IC layout. In the context of IC design, an IC “layout” is a set of geometric patterns, typically in the form of polygons, which specify the size and location of different types of material used to create semiconductor devices, and electrical connections to be formed between the devices during the fabrication of an IC. For example, a diffusion window on an IC may be represented in a layout by one or more polygons which are interpreted by a fabrication facility to mean “diffusion layer geometry.” Other layers of material and features, such as contacts and vias, may also be similarly represented in an IC layout.
The polygons in an IC layout must conform to a set of design rules which define minimum sizes for certain types of material as well as minimum spacing requirements between different types of material. The design rules also specify size and spacing requirements for other layout features such as contacts. IC layout tools can automatically identify design rule violations as the layout is generated, allowing them to be corrected before the layout is completed. Once an IC layout has been created, IC design tools can be used to test the IC layout by simulating the performance of the IC layout. Although there are many different types of IC design tools, two important types of IC design tools are IC simulation tools and IC reliability tools.
Conventional IC simulation tools combine functional device connections with physical models and parameters, such as device dimensions and junction areas, to produce simulated waveforms of current/voltage versus time, as well as frequency response, for ICs under development. IC simulation tools provide a preview of IC performance and can help identify logic and timing errors in an IC design. An example of a well known transistor level IC simulation tool is SPICE (Simulation Program for Integrated Circuit Emphasis), developed at the University of California at Berkeley.
One of the limitations of IC simulation tools is that they do not account for IC performance degradation attributable to hot carrier effects. Hot carrier effects are a well known physical phenomenon that can degrade the performance of an IC over time. Consequences of long term hot carrier effects include an increased threshold voltage, reduced transconductance and a reduction in device switching speed which can change the response of an IC and in extreme cases, cause IC failure. As device dimensions in contemporary ICs are reduced and supply voltages are less scaled hot carrier effects become more acute and can significantly decrease the lifetime of an IC.
Numerous techniques are known for reducing IC degradation attributable to hot carrier effects. For example, supply voltages can be decreased, the operation frequency of ICs can be reduced or special drain structures such as lightly-doped drain structures can be introduced. Each of these approaches is a design trade-off that can adversely affect IC performance, increase the size of the IC or add complexity to a fabrication process. To select the best approach for addressing hot carrier effects in an IC while optimizing IC performance, designers must be able to characterize and simulate hot carrier effects on ICs. In response to the need for evaluating long term hot carrier effects on semiconductor device performance, various IC reliability tools have been developed.
A few IC reliability tools have been developed to model hot carrier effects on semiconductor device performance. These tools are particularly helpful for determining hot carrier effects on semiconductor devices because determining hot carrier effects requires solving several complex equations. Specifically, calculation of the maximum electric field near the drain of a transistor is a complex procedure that requires a computer-aided solution of a two-dimensional Poisson equation.
Although IC reliability tools can provide a relatively accurate model of hot carrier effects on a single semiconductor device, they have not been successfully employed to model hot carrier effects on an entire IC because of the overwhelmingly large amount of computing resources required to model hot carrier effects for thousands or tens of thousands of devices. An example of a commercially available IC reliability simulator is BTABERT by BTA Technology, Inc., of Santa Clara, Calif. BTABERT is an IC reliability simulator that can characterize device degradation due to hot carrier effects under certain operating conditions. Once the device degradation due to hot carrier effects is characterized, aged SPICE models and aged waveforms can be generated. This approach is accurate but slow. It also has the limitation of not being able to simulate large ICs that may have millions of devices.
One approach for modeling hot carrier effects of an entire IC involves characterizing the hot carrier effects for certain “standard” devices separately and then using those standard characterizations to estimate the hot carrier effects on an entire IC. This approach requires significantly fewer computational resources than an approach that characterizes every device in an IC separately, since it assumes that all devices of a particular type are equally affected by hot carrier effects. This approach has several disadvantages. First, many ICs use multiple variations of “standard” devices to accommodate different layout topologies. These variant devices often have different hot carrier characteristics. Furthermore, even identical copies of a “standard” device may have different hot carrier characteristics because the hot carrier characteristics of a particular device depend upon the proximity of the particular device to other devices in the IC and the switching frequency of the particular devices. Consequently, the approach of approximating the hot carrier effects on an entire IC using the above approach does not provide an accurate characterization of the hot carrier effects on an entire IC.
Based on the need to simulate the hot carrier effects on an entire IC and the limitations in the prior approaches, an approach for simulating hot carrier effects on an entire IC that provides a relatively accurate characterization, while requiring relatively fewer computational resources than prior approaches, is highly desirable.
SUMMARY OF THE INVENTION
One aspect of the invention is a method for simulating hot carrier effects in an integrated circuit (IC) that contains a plurality of semiconductor devices, the method comprising the steps of: receiving IC cell data that specifies a set of one or more cells in the IC, each cell containing one or more of the plurality of semiconductor devices; generating delay data and unscaled timing data of the set of one or more cells; generating, based upon the delay data and switching activity of each cell, aged delay data that reflects time-based performance degradation of time delays for the set of one or more cells; and generating, based upon unscaled timing data that specifies timing delays associated with the set of one or more cells, scaled timing data by scaling the unscaled timing data with a delay ratio, wherein the

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