Hot-carrier degradation simulation of a semiconductor device

Details Hot-carrier degradation simulation of a semiconductor device Hot-carrier degradation simulation of a semiconductor device

2000-03-09

2003-07-01

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S018000

Reexamination Certificate

active

06587994

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on Japanese priority applications No. 11-061081 filed on Mar. 9, 1999, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to fabrication of semiconductor devices and more particularly to a hot-carrier degradation simulation of a MIS transistor for use in a fabrication process of a MIS transistor. In more detail, the present invention is related to a high-precision hot-carrier degradation simulation applicable for a wide variety of bias conditions by caking into consideration the effect of both deep surface states and shallow surface states.
MIS (metal-insulator-semiconductor)-type transistors are used extensively in various semiconductor devices including DRAMs as a fundamental active device. In a MIS transistor, it is well known that carriers are accelerated in the channel region right underneath the gate electrode, particularly in the region adjacent to the drain region called drain edge region.
When the acceleration of carriers is excessive, there are formed hot electrons in the channel region and the hot electrons thus formed are injected to the gate insulation film provided between the substrate and the gate electrode. The carriers thus injected then form surface states in the gate insulation film, wherein the surface states thus formed induce a deterioration in the threshold characteristic of the MIS transistor. Thus, it is necessary to evaluate the hot-carrier degradation of the device characteristic at the time of designing a semiconductor device by way of simulation and to modify the design as a result of the simulation.
In order to carry out such a hot-carrier degradation simulation, an accelerated degradation test has to be conducted for an actual MISFET so as to establish a hot-carrier degradation model.
In the accelerated degradation test, a predetermined drain voltage V
D
and a gate voltage V
G
are applied to the MISFET to be tested and the degradation of the device characteristic is monitored. As a result of the hot-carrier injection, there may be observed a degradation in the drain current I
d
in the form of a drain current change &Dgr;I
d
, the threshold voltage V
th
in the form of a threshold voltage change &Dgr;V
th
, transconductance gm in the form of &Dgr;g
m
, and the like.
Generally, it is accepted that the hot-carrier degradation of a MISFET is represented as
Deg(
t
)=
Kt
n
  (1)
wherein Deg(t) represents any of &Dgr;I
d
, &Dgr;V
th
and &Dgr;g
m
. In Eq.(1), the parameter t represents the stress time, which is the accumulated time in which the stress is applied to the tested MISFET.
In view of the fact that the hot carriers causing the device characteristic degradation can be measured indirectly in the form of substrate current I
SUB
, the foregoing equation (1) can be represented with the substrate current I
SUB
as follows.
Deg(
t
)=[(
I
D
/HW
)(
I
SUB
/I
D
)
m
]
n
t
n
  (2)
wherein I
D
represents the drain current during the accelerated test, that is the stressed state, W represents the gate electrode width, and H represents the fitting parameter. Further, the lifetime &tgr; of the MISFET is defined as the stress time until a drain current drop of 10% is observed in a reverse biased state.
According to Eqs.(1) and (2), it can be seen that the degradation Deg(t) is proportional to the quantity t
n
for all the biasing conditions. Further, it is reduced that the logarithmic plotting of the relationship log t−log &Dgr;Deg(t) provides a number of parallel lines. Further, the logarithmic plotting of the relationship log(&tgr;I
D
)−log(I
SUB
/I
D
) provides a single line.
FIG. 1
shows an example of the accelerated test.
During the acceleration test, a drain voltage V
D
of 3.0V and a gate voltage V
G
of 2.0V are applied to the MISFET as a DC stress, and
FIG. 1
represents the observed drain current change &Dgr;I
d
as a function of the stress time t in a logarithmic scale (log &Dgr;I
d
−log t) plot. In
FIG.1
, it should be noted that the drain current change &Dgr;I
d
is represented for various biasing conditions as indicated in FIG.
1
and is represented in the form of a normalized, dimensionless quantity. In the example of
FIG. 1
, &Dgr;I
d
and t are normalized with respect to the state of &Dgr;I
d
=1 and t=10,000 seconds, for facilitating the comparison of the plot. In the description hereinafter, it is assumed that the suffix represented in a capital letter indicates that the quantity to which the suffix is attached represents the stress condition in the acceleration test while the suffix represented in a small letter indicates that the quantity to which the suffix is attached represents the bias condition used in the measurement after the acceleration test.
Now, when the Eqs.(1) and (2) are valid, then it is predicted that all the plotting points in
FIG. 1
are supposed to align on the lines having the same slope. However,
FIG. 1
clearly indicates that the slope, and hence the exponent n of Eqs.(1) and (2), changes with the bias condition of the MISFET used at the time of the measurement. The result of
FIG. 1
thus indicates that Eqs.(1) and (2) are not valid for wide variety of biasing conditions but valid for only a limited range of biasing condition such as V
d
=V
g
=supply voltage. Further, even when the foregoing condition of V
d
=V
g
=supply voltage is satisfied, the slope, and hence the exponent n, still changes when the biasing is changed under the foregoing constraint.
FIG. 2
shows the D.C.-stress dependence of the exponent n, wherein
FIG. 2
uses a difference between the drain voltage V
D
and the gate voltage V
G
used for the D.C. stress as a horizontal axis.
Referring to
FIG. 2
, it can be seen that the value of the exponent n, and hence the slope, changes when the absolute value of V
D
or V
G
is changed, even in such a case the difference V
D
−V
G
is held constant.
FIG. 3
shows the relationship between the D.C. stress condition and the lifetime &tgr; of the MISFET, wherein
FIG. 3
defines the lifetime &tgr; as the stress time until there is observed a 10% drop of the drain current I
d
as noted before. In
FIG. 3
, the horizontal axis represents I
SUB
/I
D
, while the vertical axis represents &tgr;I
D
.
As can be seen clearly from
FIG. 3
, there appear a plurality of lines in correspondence to each of the stress conditions (V
D
−V
G
), wherein the existence of such plural lines is contradictory to the conventional model of Eqs.(1) and (2).
Thus, it is concluded that the conventional hot-carrier degradation model of Eqs.(1) and (2) cannot describe the characteristic degradation of a MISFET over a wide range of bias conditions.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful hot-carrier degradation simulation method of a semiconductor device and a fabrication process of a semiconductor device that uses such a simulation method, wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a hot-carrier degradation simulation process of a MIS transistor that takes into consideration the effect of deep surface states and shallow surface states when calculating a degradation of device characteristics.
Another object of the present invention is to provide a fabrication process of a semiconductor device including the step of determining a process condition of a MIS transistor based on a result of such a hot-carrier degradation simulation process.
Another object of the present invention is to provide a computer-readable medium storing a hot-carrier degradation simulation process of such a MIS transistor.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.


REFERENCES:
patent: 5600578 (1997-02-01), Fang et al.

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