Host microprocessor with apparatus for temporarily holding targe

Details Host microprocessor with apparatus for temporarily holding targe Host microprocessor with apparatus for temporarily holding targe

1996-07-24

1999-09-28

Palys, Joseph E.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

395394, 395561, G06F 1100

Patent

active

059580615

ABSTRACT:
Apparatus for use in a processing system having a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor including circuitry for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor, circuitry for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and circuitry for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.

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