Host interface circuit

Details Host interface circuit Host interface circuit

2001-05-30

2003-09-30

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S202000, C712S210000

Reexamination Certificate

active

06629230

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an interface circuit that performs data transmission and reception between an external host controller and a device connected to the external host controller.
BACKGROUND OF THE INVENTION
A conventional host interface circuit, which is mounted on a device connected to an external host controller such as a microcomputer, brings addresses in an internal storage space of the connected device into one-to-one correspondence with addresses in an internal storage space of the external host controller. Therefore, when the external host controller reads or writes data from/into the connected device, the external host controller generates external addresses corresponding to the respective internal addresses in the internal storage space of the connected device, thereby performing data reading or writing.
Hereinafter, a description will be given of data transmission/reception between a conventional external host controller and a device connected to the external host controller, with reference to
FIGS. 10 and 11
.
FIG. 10
is a block diagram illustrating an external host controller
100
and a device
101
connected to the controller
100
, and
FIG. 11
is a timing chart for explaining continuous access to a series of areas in an internal storage space in the connected device.
With reference to
FIG. 10
, the external host controller
100
includes a bus controller
102
, and an internal storage space
104
. The device
101
connected to the external host controller
100
includes a host interface circuit
103
, and an internal storage space
105
.
Further, a chip selection signal
106
, a read enable signal
107
, and a write enable signal
108
are outputted from the external host controller
100
to the host interface circuit
103
of the connected device
101
. An address bus
109
and a data bus
110
connect the external host controller
100
to the host interface circuit
103
of the device
101
. Further,
111
denotes an internal operating clock of the connected device
101
.
When the external host controller
100
so constructed reads data stored in the internal storage space
105
of the connected device
101
, initially, the external host controller
100
generates an external address corresponding to each of the internal addresses
113
in the internal storage space
105
of the connected device
101
, a chip selection signal
106
, and a read enable signal
107
, which signals correspond to the external address. Then, the host interface circuit
103
detects the falling edge of the read enable signal
107
from the external host controller
100
, in synchronization with the internal operation clock
111
(
112
in FIG.
11
). Thereby, the host interface circuit
103
judges that the external host controller
100
makes access to the internal storage space
105
of the connected device
101
, and generates an internal address
113
in the internal storage space
105
corresponding to the external address to perform reading of data.
For example, it is assumed that the external host controller
100
generates external addresses N, N+1, N+2, . . . corresponding to a series of areas in the internal storage space
105
of the connected device
101
, as shown in the timing chart of FIG.
11
. The host interface circuit
103
detects the falling edges of the chip selection signal
106
and the read enable signal
107
(
112
in FIG.
11
), which are supplied from the external host controller
100
operating on a clock different from the internal operation clock
111
, and judges that the external host controller
100
makes access. Then, an address generation circuit in the connected device
101
generates internal addresses s, s+1, s+2, . . . corresponding to the external addresses N, N+1, N+2, . . . , respectively, thereby performing continuous access to the serial areas in the internal storage space
105
.
Meanwhile, there is direct memory access (hereinafter referred to as DMA) as another method of making continuous access to a series of areas in the internal storage space of the device connected to the external host controller.
FIG. 12
is a block diagram illustrating a hardware structure performing DMA.
With reference to
FIG. 12
, DMA is direct data transmission/reception between an external device connected to an external host controller and a memory, without the intervention of the external host controller. To perform DMA transfer, setting on a DMA controller is carried out by software of the external host controller through the following steps: (1) setting a head address of a transfer data area on the memory, in a memory address counter; (2) setting the number of words to be transferred, in a number-of-words counter; (3) setting either “reading” or “writing” in a control register in a control circuit; (4) making a transfer start instruction.
After the above-described setting, the DMA controller increments the memory address counter while decrementing the number-of-words counter until the count of the number-of-words counter becomes 0, thereby making continuous access to a series of areas in the internal storage space of the external device connected to the external host controller.
Since, in DMA, the external host controller doesn't need to directly control data transmission/reception, the load on the external host controller is not so great. However, it is necessary to make interruption to the external host controller when DMA transfer is ended. Further, since the external host controller and the DMA controller basically operate independently from each other, there is a possibility of competition for memory access. Therefore, DMA requires a memory bus controller to arbitrate competition for memory access between the external host controller and the DMA controller.
As described above, when performing data transmission/reception between the external host controller and the device connected to the external host controller by using the conventional host interface circuit, the addresses corresponding to the internal storage space of the external host controller are brought into one-to-one correspondence with the addresses corresponding to the internal storage space of the connected device. Therefore, when the external host controller makes continuous access to a series of areas in the internal storage space in the connected device, the external host controller must generate individual external addresses corresponding to the respective internal addresses in the internal storage space of the connected device. Accordingly, signal transition occurs on the external address bus every time access is made to the internal address in the internal storage space of the connected device, resulting in power consumption due to the signal transition on the external address bus.
Further, when performing transmission/reception of plural data streams between the external host controller and the device connected to the external host controller, the external host controller must generate and manage external addresses corresponding to the internal storage space of the connected device, for every data stream to be transmitted/received, to make access to the connected device. Therefore, the processing by software of the external host controller is complicated.
On the other hand, although continuous access to a series of areas by DMA is efficient, since special DMA controller and memory bus controller are required in addition to the conventional bus controller and interface circuit, the hardware scale is increased. Further, since interruption or the like is required, the software processing is complicated.
Accordingly, if the external host controller has processing ability enough and to spare, it might be better not to use DMA. However, as mentioned above, the conventional host interface circuit has the problem of power consumption due to the signal transition on the external address bus.
SUMMARY OF THE INVENTION
The present invention is made to solve the above-described problems and has for its object to pro

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