Electrical computers and digital processing systems: memory – Address formation
Patent
1996-12-24
1999-04-27
Swann, Tod R.
Electrical computers and digital processing systems: memory
Address formation
711217, 711167, 711154, G06F 926
Patent
active
058976639
ABSTRACT:
A computer system having a bridge and I.sup.2 C EEPROMs is provided with a host I.sup.2 C controller implemented in the bridge for accelerating the reading of the I.sup.2 C EEPROMs. The host I.sup.2 C controller accelerates the reading of I.sup.2 C EEPROMs by executing current address reads of the I.sup.2 C EEPROM when a requested slave address matches a current slave address stored in a current slave address register, and the requested EEPROM address matches a current EEPROM address stored in a current EEPROM address counter. The host I.sup.2 C controller thus eliminates the use of software to track the read accesses of a plurality of masters to an I.sup.2 C EEPROM and also eliminates the use of bus command protocols to support both random reads and current address reads to an I.sup.2 C EEPROM.
REFERENCES:
"PCF8584 I.sup.2 C-bus controller", Product specification, Phillips Semiconductors, (Aug. 29, 1995).
"Microchip Non-Volatile Memory Products Data Book", Microchip Technology, Inc. (May 1995).
"Peripheral Components", Intel (1996).
"The I.sup.2 C-bus and how to use it", Phillips Semiconductors.
"System Management Bus Specification", Rev 0.95, Intel Corporation, (1994).
Compaq Computer Corporation
Langjahr David
Swann Tod R.
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