Host adapter integrated data FIFO and data cache and method...

Details Host adapter integrated data FIFO and data cache and method... Host adapter integrated data FIFO and data cache and method...

2006-04-04

2006-04-04

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S123000, C711S168000, C710S052000

Reexamination Certificate

active

07024523

ABSTRACT:
A host adapter, which interfaces two I/O buses, caches data transferred from one I/O bus to another I/O bus in a data first-in-first-out (FIFO)/caching memory. In addition, when a target device on the another I/O bus is ready to receive the data, data is transferred from the data FIFO/caching memory even though not all of the data may be cached in that memory. Hence, data is concurrently transferred to and transferred from the data FIFO/caching memory. The data transfer to the target device is throttled if cached data is unavailable in the data FIFO/caching memory for transfer, e.g., the data cache is empty for the current context.

REFERENCES:
patent: 6161169 (2000-12-01), Cheng
patent: 6167487 (2000-12-01), Camacho et al.
patent: 6216199 (2001-04-01), DeKoning et al.
patent: 6725348 (2004-04-01), Marier et al.
patent: 6748486 (2004-06-01), Burton et al.

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