Host adapter integrated circuit having autoaccess pause

Details Host adapter integrated circuit having autoaccess pause Host adapter integrated circuit having autoaccess pause

1999-04-29

2001-03-13

Myers, Paul R. (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S114000, C710S244000

Reexamination Certificate

active

06202117

ABSTRACT:

CROSS REFERENCE TO MICROFICHE APPENDICES
The microfiche appendix, which is a part of the present disclosure, is a microfiche appendix of two sheets of microfiche having a total of 71 frames. The microfiche appendix contains detailed schematics of a specific embodiment of a host adapter integrated circuit. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND INFORMATION
A personal computer typically comprises a motherboard on which a CPU, main memory, and a plurality of expansion slots are disposed. The CPU and main memory may be referred to as the “host”. In order to couple the host to a device (for example, a hard disk), a printed circuit board called a “host adapter card” is typically plugged into one of the expansion slots. The host adapter card is typically coupled to the hard disk via a ribbon cable and a bus (such as a Small Computer System Interface (SCSI) bus) and is coupled to the host via the expansion slot and a system bus (such as the Peripheral Component Interconnect (PCI) bus)). The host therefore can read data from and write data to the hard disk through the host adapter card. Many functions of the host adapter card (such as a PCI bus interface for interfacing to the host and a SCSI bus interface for interfacing with a hard disk) may be integrated into a single integrated circuit called a “host adapter integrated circuit” which is disposed on the host adapter card.
SUMMARY
A host adapter integrated circuit has circuitry which detects an attempted access of a digital resource (for example, a register of a SCSI bus interface) from an external system bus (for example, a PCI bus) and automatically generates a pause request signal to a sequencer on the host adapter integrated circuit. The pause request signal causes the sequencer to stop executing instructions. The sequencer is decoupled from the digital resource and the digital resource is coupled to the system bus. With the digital resource coupled to the system bus, the system bus cycle access of the digital resource is completed. In some embodiments, a pause acknowledge signal is generated by bus transfer logic of the sequencer indicating that the digital resource is ready to be accessed from the system bus. This pause acknowledge signal is used to generate a ready signal onto the system bus. The ready signal is an indication to the device on the system bus attempting the access that the attempted system bus cycle can be completed.


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