Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-02
2001-05-29
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C711S173000
Reexamination Certificate
active
06240482
ABSTRACT:
MICROFICHE APPENDIX
The disclosure includes one sheet of microfiche having 29 frames. The microfiche appendix contains a listing of Verilog Code for a portion of a memory port interface including a module that generates external memory address in accordance with an embodiment of the invention.
BACKGROUND
1. Field of the Invention
This invention relates to a circuit architecture that maps an internal address space into an external address space, where the mapping adapts according to the application of the circuit and according to a current operating mode of the circuit.
2. Description of Related Art
Many digital circuits access memory and other resources using addresses that identify an accessible source or destination of a digital signal. The addresses that uniquely identify the accessible sources and destinations for signals can be referred to as the external address space for the circuit. For large external address spaces, the number of address bits required to uniquely identify a specific source or destination can be relatively large. Typically, the circuit requires address buses, address registers, and associated logic having sufficient width to access any location in the local external address space. Thus, making a circuit having a large external address space increases circuit area, complexity, and cost.
To reduce the number of address bits used in a circuit, the external address space can be divided into pages with only one page being accessed at a time, and the circuit can use an internal address space that is sufficient to identify a storage location within a current page. Thus, most address buses, registers, and logic in the circuit can be limited to the number of bits required to uniquely identify a location in a page. Such circuits additionally require page selection logic, which selects the current page for accessed, but the circuit area of the page selection logic is often less than circuit area saved by the reduction in the number of address bits handled elsewhere in the circuit. Thus, a paged external address space or memory can reduce the overall circuit size and cost.
A disadvantage of a paged external address space is that not all addresses are simultaneously accessible, and accessing required information may require frequent page changes. Such page changes can slow memory access and reduce performance of a circuit. A memory architecture is desired that minimizes the number of address bits required for the internal address space of a circuit, is compatible with a large external address space, and does not require frequent page changes to locate required information.
SUMMARY
In accordance with the invention, a memory architecture for a circuit such as a host adapter provides sections of external memory used for different types of information and programmable sizes for the sections so that the circuit can adapt to different applications. Each external memory section is divided into pages, and for each section, the circuit has a range of internal addresses that maps to a current page in the external memory section. Additionally, the circuit has several operating modes and several register sets. Each mode has a set of functions that the circuit performs and a register set that the circuit can access while operating in the mode. Thus, the available register set is selected according to the operating mode of the circuit (or equivalently according to the current function of the circuit). Currently accessible pages in the memory are also selected according to the operating mode. In particular, for a section that includes one page per mode, the memory architecture can directly use a mode number to select a page in the section. Alternatively, the register sets include registers for pointers that identify pages currently accessible in the sections. When the circuit switches modes, the accessible register set changes, and changing the register set changes the pointers to those stored in the new register set Thus, the accessible pages change. Generally, which registers are in the accessible register set and the contents of accessible memory pages are selected according to the function of the mode. Accordingly, the internal address space for accessing registers and memory can be minimized since registers and memory pages that are unnecessary for the functions of a mode can be removed from the internal address space.
In one embodiment of the invention, a circuit includes a memory, several register sets, and a circuit that accesses the memory and the register sets using internal addresses. The circuit is operable in several modes, where each mode has a mapping from internal addresses to memory locations and the registers. Specifically, each register set corresponds to one of the modes and is accessible when the circuit operates in the mode corresponding to the register set. Additionally, the memory includes sections that are partitioned into pages, and the circuit accesses one page in each section using a range of internal addresses associated with the section. In at least some of the sections, the selection of the accessible page depends on the mode. For example, each register set can include a register that identifies a page in a particular section. When the circuit changes modes, a different register becomes accessible and may identify a different page in the section.
In accordance with a further aspect of the invention, the circuit may be operable simultaneously in a first mode for read access and a second mode for write access. Accordingly, the circuit can read from one set of registers and write to another set of registers to move information from one register set to another. The circuit may further include a set of global registers that the circuit unit can access in any mode. One example of a global register is a mode register that identifies a current mode in which the circuit unit is operating. The mode register can directly select currently accessible pages in one or more of the memory sections.
As another aspect of the invention, a configuration register controls sizes of the various memory sections. This allows the memory architecture to adapt the various memory sections as required for the configuration of external memory and the specific applications of the circuit.
Another embodiment of the invention is a host adapter that includes: a sequencer operable in a first mode for transfers to or from a host computer and in a second mode for transfers to or from a peripheral bus. The host adapter further includes a first register set and a second register set coupled to the sequencer for access in the first mode and the second mode, respectively. Each register set is tailored for the functions performed in the respective modes and occupies the same range of internal addresses. Accordingly, including only the necessary registers in each set reduces the range of internal addresses.
REFERENCES:
patent: 4217638 (1980-08-01), Namimoto et al.
patent: 5274834 (1993-12-01), Kardach et al.
patent: 5455919 (1995-10-01), Brewer et al.
“Memory Management and Multitasking Beyond 640K”, Bales et al, ISBN 0-8306-3476-2, 1992.*
“Intel Microprocessors, vol. II”, ISBN 1-55512-150-0, 1991.
Devanagundy Uday N.
Gates Stillman F.
Adaptec, Inc.
Millers David
Nguyen Hiep T.
Skjerven Morrill & MacPherson LLP
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