Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Patent
1997-12-30
2000-08-15
Auve, Glenn A.
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
G06F 1328
Patent
active
061050806
ABSTRACT:
A DMA controller operable within a host adapter which automatically transmits replies to an attached host system to thereby reduce overhead processing in the I/O processor of the host adapter. The DMA controller is preferably operable to perform DMA transfers in accordance with one or more scatter/gather lists descriptive of the desired data transfer. A flag bit associated with and/or contained in entries of the scatter/gather list signifies the need to transmit a reply message to the host system. The requisite reply message is transmitted to the host system by the DMA controller following the DMA transfer of the block defined by the scatter/gather list entry containing the indicator. The reply message content is determined in accordance with information associated with and/or contained in the subsequent entry of the scatter/gather list. The subsequent scatter/gather list entry includes a reference to the reply message content and a reference to the destination location to which the reply is transmitted. In the preferred embodiment, the host adapter is operable in accordance with the industry standard I2O specifications. A reply message is transmitted to the I2O compatible host system interface via I2O defined outbound queues and context structures defined in the subsequent scatter/gather list. In addition, the reply message may be either static and predefined or dynamically generated by the DMA controller. Further, the destination for the reply message may be either statically encoded in the scatter/gather list entry or may be dynamically obtained from the context structures by the DMA controller.
REFERENCES:
patent: 5542053 (1996-07-01), Blaud et al.
patent: 5708849 (1998-01-01), Coke et al.
patent: 5864712 (1999-01-01), Carmichael et al.
Holt Keith W.
Weber Bret S.
Auve Glenn A.
LSI Logic Corporation
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