Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-26
2003-01-07
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S303000
Reexamination Certificate
active
06504198
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-087402, filed Mar. 27, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a ferroelectric memory, and in particular, to a ferroelectric memory device which includes series connected memory cells each having a transistor (T) having a source terminal and a drain terminal and a ferroelectric capacitor (C) connected between the source and drain terminals, and which is hereafter named as a “series connected TC unit type ferroelectric RAM”.
Since the ferroelectric memory is capable of rewriting data stored therein in spite of the nonvolatile characteristics thereof, it is increasingly widely employed for various end-uses. However, for the purpose of further expanding the end-use thereof, it is still indispensable to minimize the structure thereof in addition to the increase of the memory capacity thereof. As for the miniaturization of the cell size of the ferroelectric memory, there have been proposed various structures such as a COP structure and the series connected TC unit type ferroelectric RAM architecture (refer to D. Takashima et al., ISSCC, February, 1999).
As shown in
FIG. 19A
, for example, in the case of the ferroelectric RAM of the conventional structure where neither the COP structure nor the series connected TC unit type ferroelectric RAM architecture is adopted, not only a contact region
103
to be connected to an upper electrode
101
or a lower electrode
102
of the capacitor, but also a connecting wiring
105
to be connected to a diffusion layer
104
are necessary. Moreover, a predetermined space is required between a contact hole of the contact region
103
and the connecting wiring
105
, and at the same time, a large number of connecting wirings
105
and hence a large number of spaces for the connecting wirings
105
are required to be provided, so that the area required to be allocated to the layout of each cell would become large inevitably. For example, when the minimum dimension to be employed in designing the ferroelectric RAM is defined as F, the cell size of
FIG. 19A
would become 8F
2
.
One of the methods which are capable of minimizing the area required for the layout of each cell is the aforementioned series connected TC unit type ferroelectric RAM architecture, the structure of which is illustrated in FIG.
19
B. This cell is formed to have a size 6F
2
wherein the upper electrode
111
of the capacitor is commonly used by a couple of neighboring cells, and two lower electrodes
112
of a couple of neighboring cells are provided to the common upper electrode
111
. Each of these electrodes
111
and
112
is connected via a contact
113
with a diffusion layer
114
. Further, this diffusion layer
114
is also commonly used by a couple of neighboring transistors Tr.
When these cells constructed as shown in
FIGS. 19A and 19B
, respectively, are compared with each other with respect to the chip area thereof, assuming that these cells are manufactured based on the same design rule, it will be found that it is possible, through the employment of the series connected TC unit type ferroelectric RAM architecture shown in
FIG. 19B
, to reduce the area of cell to about 60% of the cell of
FIG. 19A
in the case of 4M-ferroelectric RAM. Realistically however, it seems to be difficult, according to the architecture of the series connected TC unit type ferroelectric RAM shown in
FIG. 19B
, to expect any further substantial miniaturization of the cell.
With a view to overcome this limitation in the miniaturization of the cell size and to realize a further-increased miniaturization of the cell, a series connected TC unit type ferroelectric RAM architecture having a structure as shown in
FIG. 19C
has been proposed. This ferroelectric RAM architecture having such a structure can be represented by an equivalent circuit as shown in FIG.
20
. In the structure shown in
FIG. 19C
, diffusion regions
124
to be employed respectively as a source and a drain with a gate electrode G of one memory cell transistor Tr being interposed therebetween are connected via contact plugs
123
with the upper electrode
121
and lower electrode
122
of a capacitor Cf, respectively.
Each of these diffusion regions
124
is commonly used as the source and drain of transistors of the neighboring cells, thereby constituting an architecture connected with each other in the form of a chain. In this case, the COP structure is applied to both upper and lower electrodes
121
and
122
, thereby suggesting the possibility of obtaining, under ideal conditions, a most miniaturized cell size of 4F
2
as shown in FIG.
19
C.
This structure shown in
FIG. 19C
accompanies with many difficulties before it can be actually realized. For example, when tungsten which is vulnerable to oxidation is employed for the fabrication of contact plug
123
, it is required to develop a barrier film which is capable of sufficiently electrically connected with tungsten of the contact plug
123
as well as with the lower electrode
122
, and also capable of preventing the oxidation of the tungsten after the fabrication of contact plug
123
. Furthermore, there is another problem that the upper limit of the process temperature is determined depending on the barrier properties of the barrier film. Therefore, it is very difficult at present to combine the structure of
FIG. 19C
with the employment of a barrier film of SBT whose film-forming temperature is 700° C. or more.
Further, even if it is possible to apply the COP structure to the lower electrode
122
, it is unavoidable, in order to apply the COP structure also to the upper electrode
121
for the purpose of obtaining an ideal structure as shown in
FIG. 19C
, to increase the number of steps and also to increase the number of burying steps, thereby making the entire process very complicated. In particular, it becomes difficult to secure desired properties of the ferroelectric capacitor Cf. Because of these reasons, the process integration for this cell structure can be only realized with such a great sacrifice as mentioned above.
As explained above, it is required, for the realization of a cell having 4F
2
structure which enables to miniaturize the series connected TC unit type ferroelectric RAM architecture as shown in
FIG. 19C
, to adopt a construction where both upper and lower electrodes are constituted by the COP structure, i.e. a structure where the electrodes are taken up from the beneath or underside of the ferroelectric capacitor Cf. Therefore, both upper and lower electrodes
121
and
122
necessitate the provision of a conductive barrier film. However, no one has succeeded as yet to find out such an excellent barrier film that is capable of withstanding the restoring (recovery) annealing temperature with a sufficient margin.
Thus, various technical developments such as an improved low damage working process, a low damage insulation deposition technique, a short time damage restoring technique, a technique of protecting electrodes from damaging, etc. are required.
Therefore, an object of this invention is to provide a ferroelectric memory which enables to realize the miniaturization of the cell, which can be manufactured by a simple manufacturing process, and which is stable in characteristics.
Another object of this invention is to provide a method of manufacturing such a ferroelectric memory as described above.
BRIEF SUMMARY OF THE INVENTION
This invention provides a ferroelectric memory wherein a horizontal type ferroelectric capacitor is disposed immediately above a memory cell transistor, in which a pair of capacitor electrodes having a ferroelectric layer sandwiched therebetween are arranged horizontally in a direction along with a surface of a semiconductor substrate. In particular, this invention provides a ferroelectric memory which is capable of realizing an extremely miniaturized cell size without n
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Pham Hoai
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