Horizontal MOS transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S328000, C257S329000, C257S343000

Reexamination Certificate

active

06972458

ABSTRACT:
A semiconductor device includes a base P region, a source N+region, and a drain N+region formed in a surface layer portion on a principal surface in an N−silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+region in a region including the drain N+region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+region from the source N+region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.

REFERENCES:
patent: 5640034 (1997-06-01), Malhi
patent: 6118149 (2000-09-01), Nakagawa et al.
patent: 6163051 (2000-12-01), Nakagawa et al.
patent: 6278155 (2001-08-01), Okabe et al.
patent: 6452231 (2002-09-01), Nakagawa et al.
patent: 6525375 (2003-02-01), Yamaguchi et al.
patent: 6580101 (2003-06-01), Yoshida
patent: 6713814 (2004-03-01), Koscielniak
patent: 6812522 (2004-11-01), Ishihara
patent: 6835993 (2004-12-01), Sridevan et al.
patent: 2003/0141514 (2003-07-01), Yamaguchi et al.
patent: A-2001-127287 (2001-05-01), None

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