Hold time latch with decreased percharge node voltage leakage

Details Hold time latch with decreased percharge node voltage leakage Hold time latch with decreased percharge node voltage leakage

2005-12-20

2005-12-20

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

C326S098000, C326S121000

Reexamination Certificate

active

06978387

ABSTRACT:
A dynamic logic hold time latch (20). The latch comprises a first phase circuit (12′) operable in a precharge phase and an evaluate phase and a second phase circuit (22) operable in a precharge phase and an evaluate phase. The precharge phase and the evaluate phase of the second phase circuit are out of phase with respect to the precharge phase and the evaluate phase of the first phase circuit. The first phase circuit comprises a precharge node (12′PN) to be precharged to a precharge voltage during the precharge phase of the first phase circuit and operable to be discharged during the evaluate phase of the first phase circuit. The first phase circuit also comprises an output (12′OUT) for providing a signal in response to a state at the precharge node of the first phase circuit. The second phase circuit comprises a precharge node (14′PN) to be precharged to the precharge voltage during the precharge phase of the second phase circuit and operable to be discharged during the evaluate phase of the second phase circuit. The second phase circuit also comprises a conditional discharge path (14′L, 14′DT) connected to the precharge node of the second phase circuit and operable, during the evaluate phase of the second phase circuit and in response at least in part to the output of the first phase circuit, to conditionally couple the precharge node of the second phase circuit to a voltage different than the precharge voltage. The second phase circuit also comprises voltage maintaining circuitry (22Kp1, 22Kp2), coupled to receive the output of the first phase circuit, for coupling the precharge voltage to the precharge node of the second phase circuit during the evaluate phase of the second phase circuit in response to the output of the first phase circuit providing a first value.

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Atila Alvandpour, et al., “A Low-Leakage Dynamic Multi-Ported Register File in 0.13βm CMOS” Proceedings of the 2001 International Symposium on Low Power Electronics and Design, pp. 68-71, Aug. 6, 2001.

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