Hold time error correction method and correction program for...

Details Hold time error correction method and correction program for... Hold time error correction method and correction program for...

2006-01-24

2006-01-24

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06990646

ABSTRACT:
A hold time error list, having for each hold time error path a hold time error value satisfying plural timing constraints, and more specifically a maximum hold time error value for each of timing constraints, as well as a setup time margin map allocating to path a setup time margin satisfying plural timing constraints for each setup time error path, and more specifically minimum value of setup time margins for the same path for each timing constraint, are generated. Also, referring to this setup time margin map, delay buffers, which reduces or eliminates hold time error of hold error list, and a delay of which is within the range of delay amounts and positions equal to or lower than the setup time margin, are inserted. Referring to the setup time margin map, it is possible to insert delay buffer to correct hold time error without causing new setup time errors.

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