Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
1998-12-15
2001-04-17
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C377S107000
Reexamination Certificate
active
06219798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a counter, and more particularly, to a hold/reset mode selection counter.
2. Background of the Related Art
FIG. 1
is a schematic block diagram of a related art counter. As shown in
FIG. 1
, a plurality of counter blocks CNT
1
-CNT
5
each has a count input terminal CI receiving a count enable signal CNTEN, a clock input terminal CP receiving an external clock signal CLK and respectively output a decode output value Q
0
-Q
4
. The plurality of counter blocks CNT
1
-CNT
5
are connected in series. Each count input terminal CI of the counter blocks CNT
1
-CNT
5
receives a count output signal CO from the previous counter block. In addition, a reset input terminal CDN of each of the counter blocks CNT
1
-CNT
5
is reset by receiving a reset signal RS.
FIG. 2
is a circuit diagram of an ith counter block CNT(i) of the counter blocks CNT
1
-CNT
5
in FIG.
1
. The ith counter block CNT(i) is composed of an inverter INV
1
inverting a count output signal CO(i−1) from a previous counter block CNT(i−1) a double input multiplexor MUX and a JK flipflop JKF. The JK flipflop JKF has a first input terminal J receiving the count output signal CO(i−1) from the previous counter block CNT(i−1), a second input terminal K receiving an output signal from the inverter INV
1
, a clock input terminal CP receiving an external clock signal CLK, the reset input terminal CDN receiving the reset signal RS and outputting an output value Q(i). The double input multiplexor MUX is enabled by the count output signal CO(i−1) from the previous counter block CNT(i−1). The double input multiplexor MUX has a first input terminal CI
0
connected with ground VSS, a second input terminal CI
1
receiving the output value Q(1) from the JK flipflop JFK and outputs a count output signal CO(i).
The operation of the related art counter of
FIG. 1
will now be described. First, when the two input terminals J, K of the JK flipflop JKF of the counter block CNT(i) receive different inputs, the JK flipflop JKF holds or transits a previous value at each rising edge of the external clock signal CLK. Thus, when the first and second input terminals J, K of the JF flipflop JKF receive a high-level signal and a low-level signal, respectively, the output value Q is transited. However, when the first and second input terminals J, K of the JF flipflop JKF receive a low-level signal and a high-level signal, respectively, the JF flipflop JKF holds the previous value.
The multiplexor MUX of the counter block CNT(i) generates the count output signal CO(i), which is supplied to the count input terminal CI of a next counter block CNT(i+1). Only when the count output signal CO(i−1) of the previous counter block CNT(i−1) of the counter block CNT(i) is a high level, the output value Q(i) from the counter block CNT(i) is identical to the count output signal CO(i). Thus, when output values from the counter blocks CNT
1
-CNT
5
are [00010], subsequent output values are prevented from becoming [00111], and instead become [00011].
Accordingly, when the count enable signal CNTEN is a high level, the related art counter in
FIG. 1
counts from [00000] to [11111] and is reset by the reset signal RS. The related counter counts up to and holds a predetermined count value and waits for a new control signal holding the value. However, as described above, the related art counter has various disadvantages. The related art counter may have a redundant desirable counter value. In addition, the related art counter is not capable of determining whether to continue counting from a suspended point or to restart counting.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a counter that substantially obviates at least one of the problems due to the limitations and disadvantages of the related art.
Another object of the present invention is to provide a hold/reset mode selection counter that reduces power consumption by performing a counting operation only when necessary.
Another object of the present invention is to provide a hold/reset mode selection counter that simplifies a circuit by eliminating a redundant counter decode signal and selects an operation mode using a single control signal.
Another object of the present invention is to provide a hold/reset mode selection counter that does not unconditionally count in accordance with an enable signal or perform a circular counting operation.
Another object of the present invention is to provide a hold/reset mode selection counter that performs counting and resetting operations only when necessary and reduces a number of counter blocks.
To achieve at least these objects and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a hold/reset mode selection counter includes a counter unit performing an actual counting, a mode selection unit detecting a length of a high level state of a count enable signal and resetting the counter unit, a control unit enabling or disabling the counter unit and a detection unit detecting a desirable count value and holding the counter unit.
To further achieve the above objects in a whole or in parts, a counter according to the present invention is provided that includes a counter unit that includes a plurality of counter blocks; a mode selection unit that sets one of a first mode and a second mode of the counter circuit by detecting a control signal; and a control unit that controls the counter unit, wherein the control unit operates the counter unit according to the counter circuit mode when a prescribed counter unit value is reached.
To further achieve the above objects in a whole or in parts, a hold/reset mode selection counter according to the present invention is provided that includes a counter unit that includes a plurality of counter blocks that output an output value; a mode selection unit that outputs a mode selection signal; a control unit coupled to the counter unit and the mode selection unit that enables and disables the counter unit; and a detection unit that detects when the counter reaches a prescribed counter value and outputs a detection signal, wherein the control unit operates the counter unit according to the mode selection signal when the detection signal is received.
To further achieve the above objects in a whole or in parts, a method of operating a counter according to the present invention is provided that includes initiating a counter using a count enable signal; incrementing the counter based on a clock signal; determining whether an output value of the counter equals a prescribed value; repeating the incrementing and determining steps when the output value does not equal the prescribed value, and wherein the counter is held when the output value equals the prescribed value; judging whether a prescribed state of the count enable signal exceeds an interval; and restarting the counter at the prescribed value when the prescribed state of the count enable signal is judged not to exceed the interval, and returning to the initializing step when the prescribed state of the count enable signal exceeds the interval.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 5321344 (1994-06-01), Ott et al.
patent: 5383230 (1995-01-01), Fuse et al.
patent: 5481581 (1996-01-01), Jones, Jr.
patent: 5557781 (1996-09-01), Stones et al.
patent: 5
Fleshner & Kim LLP
Heckler Thomas M.
Hyundai Electronics Industries Co,. Ltd.
LandOfFree
Hold-reset mode selection counter and operation method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hold-reset mode selection counter and operation method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hold-reset mode selection counter and operation method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2448431