Hit determination circuit for selecting a data set based on miss

Details Hit determination circuit for selecting a data set based on miss Hit determination circuit for selecting a data set based on miss

1997-05-30

1999-10-19

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711154, G06F 1208

Patent

active

059705094

ABSTRACT:
For use in an x86-compatible processor having a translation look-aside buffer (TLB) and an associated cache with first and second ways, a hit indication circuit for, and method of, indicating when a hit has occurred in the first way of the cache and a computer system employing the system or the method. In one embodiment, the circuit includes: (1) a comparator circuit, associated with the second way of the cache, that compares addresses stored in the TLB and the second way and activates a miss signal when a cache miss is detected with respect to the second way and (2) a selection circuit, associated with the first way of the cache, that receives the miss signal from the comparator circuit and generates, in response thereto, a hit signal for the first way, the comparator and selection circuits cooperating to base a cache hit in the first way on the cache miss in the second way.

REFERENCES:
patent: 5353424 (1994-10-01), Partovi et al.
patent: 5539892 (1996-07-01), Reininger et al.
patent: 5553262 (1996-09-01), Ishida et al.
patent: 5640532 (1997-06-01), Thome et al.
patent: 5732242 (1998-03-01), Mowry
patent: 5784589 (1998-07-01), Bluhm

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