Hit bit for indicating whether load buffer entries will hit a ca

Details Hit bit for indicating whether load buffer entries will hit a ca Hit bit for indicating whether load buffer entries will hit a ca

1997-10-07

1998-09-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711140, 711131, G06F 1200

Patent

active

058025758

ABSTRACT:
A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered. A method and apparatus for servicing LOAD instructions, in which the access of the data array portion of a cache and the tag array portion are decoupled, allows the delayed access of the data array after a LOAD has been delayed in the load buffer without reaccessing the tag array.

REFERENCES:
patent: 5056002 (1991-10-01), Watanabe
patent: 5283890 (1994-02-01), Petolino, Jr. et al.
patent: 5404484 (1995-04-01), Schlansker et al.
patent: 5467473 (1995-11-01), Kahle et al.
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5542062 (1996-07-01), Taylor et al.

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