History-based bus arbitration with hidden re-arbitration during

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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Details

710107, 710108, 710110, 710112, 710116, 710119, 710123, 710240, 710241, 710244, 711146, G06F 1336

Patent

active

060731990

ABSTRACT:
An arbiter uses a history based bus arbitration scheme to more fairly allocate a shared resource among multiple devices. The arbiter uses a history queue to dynamically update the priorities of the devices using the shared resource, and makes the grant decision in a single calculation using the combination of the history queue and requests from bidding devices. The priority for granting master to each device is dynamically modified so that the least recently serviced requestor will be granted the shared resource. A hidden arbitration scheme provides more fair history based resource allocation. A bus retry scheme demotes priority for processing devices that are assigned bus master but do not perform bus operations within a predetermined number of clock cycles. The arbiter also prevents bus grants during hot swap operations.

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