Highly integrated semiconductor memory device with triple well s

Details Highly integrated semiconductor memory device with triple well s Highly integrated semiconductor memory device with triple well s

1992-12-23

1994-12-13

Nguyen, Viet Q.

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365174, 365181, 257371, 257369, 257368, 257296, H01L 2702, H01L 2710

Patent

active

053734769

ABSTRACT:
A highly integrated semiconductor memory device, such as a DRAM, is provided with a unique triple-well structure which results in reduced junction capacitance of transistors and a smaller body effect. The semiconductor memory device comprises first and second wells of a first conductivity type and a third well of a second conductivity type formed in a semiconductor substrate of the first conductivity type. The first well is formed in the third well and the first well and the second well are connected to receive a ground level Vss well bias voltage and a negative level V.sub.BB well bias voltage, respectively. A plurality of MOS transistors of the first conductivity type are formed in the third well and at least two series-connected MOS transistors of the second conductivity type are formed in the first well. A plurality of MOS transistors of the second conductivity type and a plurality of memory cells are also formed in the second well.

REFERENCES:
patent: 4907058 (1990-03-01), Sakai
patent: 5079613 (1992-01-01), Sawada et al.
patent: 5148255 (1992-09-01), Nakazato et al.
patent: 5179539 (1993-01-01), Horiguchi et al.
patent: 5281842 (1994-01-01), Yasuda et al.

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