Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-29
2003-09-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C438S201000, C438S211000, C438S257000
Reexamination Certificate
active
06624464
ABSTRACT:
This application claims priority from the Korean Patent Application No. 00-67468, filed Nov. 14, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to an integrated non-volatile memory cell array and, more particularly, to a highly integrated non-volatile memory cell array having a high program speed.
BACKGROUND OF THE INVENTION
Semiconductor devices are largely classified into random access memories (RAMs), such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), and read only memories (ROMs). RAMs input and output data at a high speed but lose data when power is turned off. ROMs on the other hand, input and output data at a low speed but maintain the data even when power is turned off. Electrically erasable and programmable ROMs (EEPROM) are a type of ROM capable of electrically erasing data. Flash memory is a developed form of the EEPROM, that can also be electrically erased. Flash memory uses so-called Fowler-Nordheim tunneling or hot electron technology to control the input and output of data.
FIGS. 1A and 1B
are a perspective view and a cross-sectional view, respectively, of a non-volatile memory cell structure of a common flash memory device. Referring to
FIGS. 1A and 1B
, the non-volatile memory cell has a stack type gate structure. Field oxide layers
110
are spaced apart from each other on a semiconductor substrate
100
. A tunnel oxide layer
120
, floating gates
130
and
140
, a dielectric layer
150
, and a control gate
180
are sequentially formed over an electrically active region (not shown) between the field oxide layers
110
. A first floating gate
130
is restricted to an electrically active region so that a critical dimension thereof is equal to a critical dimension of the electrically active region. A second floating gate
140
extends to the field oxide layers
110
so that a critical dimension thereof is larger than that of the first floating gate
130
.
As shown in
FIGS. 1A and 1B
, the floating gates
130
and
140
have a two-electrode-structure to increase a coupling ratio. The coupling ratio, which denotes a ratio of voltage applied to a control gate and voltage coupled to a floating gate, is a key parameter in storing and erasing data in the flash memory. The programming coupling ratio (C/R
p
) is indicated as Equation 1.
C
/
R
p
=
C
ono
C
ono
+
C
tun
Equation
1
wherein:
C
ono
indicates capacitance of a dielectric layer; and
C
tun
indicates capacitance of a tunnel oxide layer.
The erasing coupling ratio (C/R
e
) is indicated as Equation 2.
C
/
R
e
=
C
tun
C
ono
+
C
tun
Equation
2
The programming coupling ratio calculated by Equation 1 is generally kept between 0.55-0.65. The erasing coupling ratio is approximately 0.35-0.45. To increase the programming coupling ratio, it is necessary to increase the capacitance (C
ono
) of the dielectric layer
150
. A stack layer of oxide
itride/oxide having a larger dielectric constant than the tunnel oxide layer
120
is used as the dielectric layer
150
. Another method of increasing the coupling ratio is to increase a contact area of the dielectric layer
150
and the second floating gate
140
.
Meanwhile, capacitance of the dielectric layer
150
is proportional to the contact area of the second floating gate
140
and the dielectric layer
150
. It is important, therefore, to keep the contact area of the second floating gate
140
uniform in the memory cell array. If the capacitance in the cell is changed, the coupling ratio also changes every cell when data is stored and erased. Consequently, each cell does not consistently operate at a predetermined voltage. To prevent malfunction during programming or erasing, the cell is programmed more frequently resulting in increased programming time thereby lowering device performance.
Referring to a conventional flash memory cell shown in
FIG. 1B
, a width W of the second floating gate
140
overlaps field oxide layers
110
to widen the contact area of the floating gate
140
and the dielectric layer
150
so that a height H is smaller than the width W. In such a structure, the upper area of the second floating gate
140
contacts the dielectric layer
150
. Consequently, the width W of the second floating gate
140
of the conventional flash memory cell is sensitive to critical dimension error due to parameters in photolithographic and etching processes for patterning the second floating gate
140
.
Generally, in photolithographic and etching processes there are a lot of parameters causing critical dimension error, for example, a proximity effect generated in the manufacturing of the mask of the photolithographic process and a loading effect generated in the etching process. It is difficult to control these parameters due to design rule reduction and pattern density increases in semiconductor circuits.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the disadvantages associated with prior art non-volatile memory cells.
It is another object of the present invention to provide a non-volatile memory cell array having a high program speed owing to low coupling ratio variability between memory cells.
Accordingly, to achieve the above object, there is provided a non-volatile memory cell array comprising protruding field oxide layers arranged on a substrate at predetermined intervals. Electrically active regions are separated from each other by the protruding field oxide layers. A plurality of field oxide layers and a first floating gate is sequentially stacked, the field oxide layers and the first floating gate being restricted on the respective electrically active regions. A plurality of second floating gates is electrically connected to the respective first floating gates, the second floating gates having a width which extends to the adjacent field oxide layers on either side. Slanted side walls cause the width to narrow towards an upper surface and a height from the field oxide layers is larger than the width of the upper surface. A dielectric layer is formed on the plurality of second floating gates. A continuous control gate is formed on the dielectric layer.
According to an embodiment of the present invention, a distance between the upper surfaces of two adjacent second floating gates is 1.4-1.8 times a distance between the adjacent second floating gates on the gate oxide layer. The distance between the upper surfaces of two adjacent second floating gates is equal to the width of the first floating gates. The width of the upper surfaces of the second floating gates is larger than or equal to the width of the first floating gates.
According to an embodiment of the present invention, the ratio of the height of the upper surfaces of the second floating gates from the field oxide layers into the width of the upper surfaces of the second floating gates is 1-3. In one embodiment, the height of the upper surface of the second floating gate from the field oxide layer is approximately 2000-4000 Å.
According to an embodiment of the present invention, the side walls of the plurality of the second floating gates are slanted at 60-80°.
In a non-volatile memory cell array of the present invention, the width of the second floating gate is narrow and the height thereof is large. Consequently, the difference in the coupling ratio between the memory cells is low, thereby improving program speed in programming or erasing. And the side walls of the second floating gate of the present invention are slanted, thereby forming a highly integrated non-volatile memory cell array.
REFERENCES:
patent: 4874715 (1989-10-01), Paterson
patent: 5138573 (1992-08-01), Jeuch
patent: 5973353 (1999-10-01), Yang et al.
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6403421 (2002-06-01), Ikeda et al.
patent: 11-054633 (1999-02-01), None
English language of Japanese Patent No. 11-54633.
Chang Sung-Nam
Choi Jung-Dal
Lee Won-Hong
Park Kyu-Charn
Shin Kwang-Shik
Marger & Johnson & McCollom, P.C.
Nelms David
Tran Long
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