Highly effective charge pump employing NMOS transistors

Details Highly effective charge pump employing NMOS transistors Highly effective charge pump employing NMOS transistors

1999-10-28

2001-12-04

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06326833

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electric circuit, and more particularly, to a charge pump for generating a high voltage required for an internal circuit of a semiconductor memory device.
2. Description of the Related Art
As the need for larger dynamic random access memory (DRAM) integrated circuits (ICs) increases, the integration of the DRAM IC increases, and the amount of control circuitry required on the DRAM increases. Accordingly, the DRAM ICs consume more power. When such semiconductor memory devices are in portable systems, the devices consume a large amount of power and quickly drain the batteries of the portable systems. Accordingly, the increasing integration of semiconductor memories shortens the time for which the portable system can operate. In response, the supply voltage of semiconductor memory devices has been decreased to decrease power consumption. For example, in the past, semiconductor memory devices had a supply voltage of 5.0 volts. However, more recent semiconductor memory devices use a supply voltage of 3.3 volts, and development of devices having supply voltages lower than 3.3 volts is continuing.
A Metal oxide semiconductor (MOS) transistors are common in semiconductor memory devices. When the supply voltage passes through an n-channel MOS (or NMOS) transistor, the voltage drops. More specifically, when the supply voltage is applied to the drain and the gate of an NMOS transistor, the resulting source voltage is less than the supply voltage by the threshold voltage of the NMOS transistor. Using a gate voltage that is higher than the supply voltage can keep the gate-to-source voltage equal to the threshold voltage of the NMOS transistor and provide a source voltage equal to the supply voltage.
In general, charge pumps include a plurality of MOS transistors for generating and transmitting a high voltage. It is possible to obtain a higher voltage from the charge pumps by reducing the loss of voltage due to the threshold voltage of the MOS transistors in transmitting the high voltage. However, efficient charge pump circuits are sought and are essential for semiconductor memory devices that operate at voltages at or below 2.5 volts.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a charge pump circuit generates a higher voltage by reducing the loss due to the threshold voltage of MOS transistors. The charge pump circuit can be employed in a semiconductor memory device for generating a high voltage from a low power supply voltage.
A charge pump circuit according to an embodiment of the present invention includes a pulse generator, a first voltage pumping unit, a second voltage pumping unit, and a voltage transmitting unit. The pulse generator generates a pulse signal in response to an external control signal. The first voltage pumping unit generates a first high voltage of a predetermined level in response to the control signal and the pulse signal. The second voltage pumping unit generates a second high voltage of the same level as the first high voltage in response to the control signal and the pulse signal. The voltage transmitting unit receives the first high voltage and outputs the first high voltage when the second high voltage is applied.
The pulse generator preferably generates a logic low level pulse signal when the control signal toggles from a first level to a second level.
The first voltage pumping unit preferably generates a third high voltage when the pulse signal is generated and the first high voltage, which is higher than the third high voltage, immediately after the pulse signal has disappeared. The second voltage pumping unit preferably generates a fourth high voltage when the pulse signal is generated and the second high voltage, which is higher than the fourth high voltage, immediately after the pulse signal has disappeared.
According to the present invention, it is possible to obtain a high voltage without the voltage drop due to the threshold voltage of an NMOS transistor.


REFERENCES:
patent: 5408140 (1995-04-01), Kawai et al.
patent: 5701096 (1997-12-01), Higashiho
patent: 5774012 (1998-06-01), Im
patent: 5861772 (1999-01-01), Lee
patent: 6055193 (2000-04-01), Manning et al.

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