Higher voltage transistors for sub micron CMOS processes

Details Higher voltage transistors for sub micron CMOS processes Higher voltage transistors for sub micron CMOS processes

2000-09-26

2003-04-15

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000, C257S408000, C257S502000

Reexamination Certificate

active

06548874

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of MOSFET transistors and more specifically to an integrated high voltage drain extended transistor for CMOS applications.
BACKGROUND OF THE INVENTION
In integrated circuits there is often the need to have a number of different operating voltages. Circuits that use transistors with gate lengths less than 0.25 um typically operate at voltages less than 2.5 volts. For input-output operations (i.e., connection to circuits external to the chip) longer gate length transistors (>0.3 um) typically operate at about 2.5V to 3.3V. In some instances such as disk drive controllers, the circuits might require a 5 volt Signal. In these cases, transistors capable of operating at high voltages are required. A transistor suitable for use at high voltages in integrated circuits is a drain extended (DE) transistor. Drain extended transistors may also be used in applications where the voltage on the drain exceeds the normal voltage rating of the gate oxide. Drain extended transistors differ from regular self aligned poly-silicon gate transistors in that they use a very lightly doped extension region adjacent to the drain that depletes at high drain voltages. This allows much of voltage to be dropped across the silicon, reducing the electric field across the gate oxide to a safe level. Drain extended transistors allow operation at several times the rated voltage of core transistors, can handle analog signals of several volts, are suitable for power amplifiers and power conditioning circuits, and are generally more robust than conventional transistors having the same thickness of gate oxide. In particular, it is not necessary to add extra drain implants to control channel hot carrier (CHC) effects, and the higher breakdown voltage simplifies electrostatic discharge (ESD) protection; for example it is not normally necessary to include the resistors commonly required in series with application specific integrated circuits (ASIC) outputs.
Typically, to incorporate DE transistors into a CMOS integrated circuit, additional and special processes are required. These processes usually add cost and complexity to producing the integrated circuit. In the instant invention, DE transistor structures and processing methods are described that allow the incorporation of high voltage DE transistors into integrated circuits where the core CMOS transistor has a gate length of <0.30 um without introducing added processing complexity.
SUMMARY OF THE INVENTION
The integrated DE transistor structures described herein according to the instant invention can be fabricated using technology suitable for fabricating transistors with sub micron gate lengths.
An embodiment of the instant invention is an integrated circuit drain extended transistor comprising: a semiconductor substrate containing a, first well region adjacent to a second well region; a transistor gate overlying said first well region and said second well region; a transistor source region of a first conductivity type adjacent to said transistor gate and contained in said first well region; and a transistor drain region of a first conductivity type contained in said second well region.
Another embodiment of the instant invention is an integrated circuit drain extended transistor comprising: a semiconductor substrate containing a first well region; a transistor gate partially overlying said first well region and said semiconductor substrate; a transistor source region of a first conductivity type adjacent to said transistor gate and contained in said semiconductor substrate; and a transistor drain region of a first conductivity-type contained in said first well region.


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patent: 5612643 (1997-03-01), Hirayama
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