Higher performance CMOS on (110) wafers

Details Higher performance CMOS on (110) wafers Higher performance CMOS on (110) wafers

2011-06-28

2011-06-28

Luu, Chuong A (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S198000, C257SE23141, C257SE21240

Reexamination Certificate

active

07968946

ABSTRACT:
A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.

REFERENCES:
patent: 7160769 (2007-01-01), White et al.
patent: 2004/0142545 (2004-07-01), Ngo et al.
patent: 2005/0260806 (2005-11-01), Chang et al.
patent: 2006/0220113 (2006-10-01), Tamura et al.
patent: 2006/0267100 (2006-11-01), Noguchi et al.
patent: 2007/0252144 (2007-11-01), Peidous et al.
patent: 2007/0269963 (2007-11-01), Cheng et al.
patent: 2008/0020515 (2008-01-01), White et al.
Mizuno, T. et al., “(110)-Surface Strained-SOI CMOS Devices” IEEE Transactions on Electron Devices, Mar. 2005, pp. 367-374, vol. 52, No. 3.
Mizuno, T. et al., “(110)-Surface Strained-SOI CMOS Devices with Higher Carrier Mobility” Symposium on VLSI Technology Digest of Technical Papers, Jun. 10-12, 2003, pp. 97-98.
Nakamura, H. et al., “Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate” Japanese Journal of Applied Physics, 2004, pp. 1723-1728, vol. 43, No. 4B.
A. Shimizu et al. “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, 2001 IEEE IEDM Tech. Digest, pp. 433-436.
Shinya Ito et al. “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, 2000 IEEE IEDM Tech. Digest, pp. 247-250.
F. Ootsuka et al. “A Highly Dense, High-Performance 130 nm Node CMOS Technology for Large Scale System-on-a-Chip Applications”, 2000, IEEE IEDM Tech. Digest, pp. 575-578.
H.S. Yang et al. “Dual Stress Liner for High Performance sub-45 nm Gate Length SOI CMOS Manufacturing”, IEEE IEDM 2004 Tech. Digest, pp. 1075-1077.

Affiliated with

Also associated with

Rating

Higher performance CMOS on (110) wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Higher performance CMOS on (110) wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Higher performance CMOS on (110) wafers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2661428