Higher order digital phase loop filter

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

375350, 327156, H04L 2706

Patent

active

057745129

DESCRIPTION:

BRIEF SUMMARY
This invention relates to circuitry for recovering pulse amplitude modulated, PAM, signals, and more particularly to loop filters utilized in such systems.


BACKGROUND OF THE INVENTION

PAM signals occur in several forms such as Quadrature Amplitude Modulated (QAM), Phase Shift Keying (PSK), and Quadrature Phase Shift Keying (QPSK), for example, the information of which are characterized by constellations representing a fixed number of discrete amplitude values. Recovery of the transmitted information requires recovery of the signal modulation carrier with appropriate phase control to insure proper orientation of the constellation. Typical PAM signal recovery systems are described by Lee and Messerschmitt in chapter 14 of DIGITAL COMMUNICATION, Kluwer Academic Pub., Boston Mass., 1992, an example of which is illustrated in FIG. 1 herein.
The FIG. 1 apparatus includes a source of PAM signal (not shown) which is applied to a mixer 11. Mixer 11 may be a complex multiplier, having a first input port for receiving the PAM signal and a second input port for applying a recovered carrier signal. The mixer 11 provides a baseband signal to a phase circuit including a slicer 12 and a decision circuit 13. The decision circuit 13 determines the difference between the amplitude of the received signal and the amplitude of the most probable constellation value, and outputs this difference as an error e. The combination of the elements 11, 12 and 13 form one of many alternative phase detectors (10). The output of the phase detector is applied to a loop filter 14, which is incorporated to provide a measure of noise immunity and to establish the system timing capture parameters. The output of the loop filter is a control signal, C, which is coupled to control a controlled oscillator 15. If the mixer 11 is realized in analog form the oscillator 15 may be an analog voltage controlled oscillator arranged to provide two signals having a 90 degree phase relation. Alternatively, if the mixer is realized in digital form (i.e., to process digital PAM signal) the oscillator may be a controlled discrete time oscillator DTO.
FIG. 2 illustrates a known second order loop filter circuit which, may be implemented for the filter 14 in FIG. 1. This fiter is shown realized with digital circuit elements and presumed to operate in sampled data manner. In FIG. 2, the error signal e from the phase detector is applied to first and second scaling circuits 23 and 24 which respectively weight the error signal by weighting factors K1 and K2. Error signal samples which are weighted in element 23 are delayed one sample period in delay element 22 and applied to an adder 20. Error signal samples which are scaled in element 24 are applied to an integrator including a signal summing circuit or adder 25 and a one sample period delay element 26 coupled between the output port of the adder 25 and one of its input ports. The output signal from the integrator is applied to a second input port of the adder 20 via a limiter circuit 27.
It will be recognized by those skilled in filter design that the upper circuit path provides a response to instantaneous signal changes while the lower circuit path provides a response to longer term signal trends. In the steady state the phase error is zero or very small, and the transfer function H(z) of the FIG. 2 circuit may be represented by the equation; the output of the integrator is sufficiently small that no signal limiting is incurred. However, if there is significant noise in the received signal, the noise will be reflected in the error signal, and the output of the integrator may be limited. Assume that the limiting value is K3. When limiting occurs the transfer function of the loop filter becomes; as false lock. However, when the system is operating in the limiting mode, the term K3 will normally dominate which results in undesirably slow response times.
The present invention is intended to incorporate the advantageous aspects of incorporating the effects of a limiter in a loop filter without incurring the undesirable

REFERENCES:
patent: 3967102 (1976-06-01), McCown
patent: 4356558 (1982-10-01), Owen et al.
patent: 4594556 (1986-06-01), Ohta
patent: 4604583 (1986-08-01), Aoyagi et al.
patent: 4920278 (1990-04-01), Nawata
patent: 4985900 (1991-01-01), Rhind et al.
patent: 5093847 (1992-03-01), Cheng
patent: 5471508 (1995-11-01), Koslov
patent: 5524126 (1996-06-01), Clewer et al.
patent: 5604741 (1997-02-01), Samueli et al.
patent: 5661765 (1997-08-01), Ishizu
patent: 5675612 (1997-10-01), Solve et al.

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