High-κ capped blocking dielectric bandgap engineered...

Details High-κ capped blocking dielectric bandgap engineered... High-κ capped blocking dielectric bandgap engineered...

2008-07-30

2010-10-19

Soward, Ida M (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S325000, C257S406000, C257S411000, C257SE29132, C257SE29133, C257SE29162, C257SE29164, C257SE29165

Reexamination Certificate

active

07816727

ABSTRACT:
A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

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