High-voltage transistor with multi-layer conduction region

Details High-voltage transistor with multi-layer conduction region High-voltage transistor with multi-layer conduction region

1999-02-05

2001-03-27

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S339000, C257S340000

Reexamination Certificate

active

06207994

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to high voltage field-effect transistors. More specifically, the present invention relates to high voltage field-effect transistor structures that include an insulated gate field-effect transistor in series with a junction field-effect transistor.
BACKGROUND OF THE INVENTION
It is conventional to construct a high-voltage, insulated-gate, field-effect transistor (HVFET) having a high breakdown voltage and a low “on-state” resistance. To accomplish this end, practitioners in the art have used an insulated gate field-effect transistor (IGFET) placed in series with a high-voltage junction field-effect transistor (JFET). Such a transistor is capable of switching at high voltages, has low values of on-state resistance, and has insulated-gate control. Moreover, the HVFET may advantageously be fabricated near low voltage logic transistors on a single integrated circuit chip to form what is commonly referred to as a power integrated circuit (PIC).
One goal in the art is to produce a transistor with a high breakdown voltage (V
bd
) using as small a surface area as possible. The HVFET must provide a V
bd
that is above the minimum allowed for a given application. Realizing high V
bd
in a small area reduces the cost of the PIC. Traditional HVFET devices with a high breakdown voltage require large amounts of silicon area and are expensive to fabricate.
It is also desirable to fabricate HVFETs that occupy as small a surface area as possible to realize a given on-state resistance. The figure of merit often used is known as specific on-resistance (R
sp
), which is the product of on-state resistance and surface area. A lower R
sp
allows a smaller HVFET transistor to be used to meet the on-state resistance requirements of a given application, which reduces the area and, respectively, the cost of the PIC.
Another goal in the art is to provide a highly manufacturable HVFET design that consistently delivers the required combination of V
bd
and R
sp
over a range of normal process variances. To realize this goal, the manufacturing process should introduce minimal variance in the critical device parameters, and the HVFET should exhibit minimal sensitivity to process variations.
To try to achieve the aforementioned goals, researchers and engineers have experimented with a variety of different device structures. For example, a lateral HVFET, is disclosed in “High Voltage Thin Layer Devices (RESURF Devices),” by Appels and Vaes, IEDM Tech. Digest, pp. 238-241, (1979). This device is fabricated in accordance with the Reduced Surface Field (RESURF) principal, in which an extended drain region is used to support the high off-state voltage. The RESURF principal, however, mandates that the charge in the extended drain region, which serves as the channel of a lateral junction field-effect transistor (JFET), be carefully controlled to obtain high V
bd
. To keep the maximum electric field below the critical field at which avalanche breakdown occurs, the amount of charge in the JFET channel is typically limited to a maximum of about 1×10
12
cm
−2
. When the HVFET is in the “on” state, the resistance of the JFET channel constitutes a large portion of the on-state resistance of the HVFET. Therefore, the limitation on the maximum charge in the JFET channel also sets the minimum specific on-resistance of the device.
A HVFET having an extended drain region with a top layer of a conductivity type opposite that of the extended drain region is disclosed in U.S. Pat. No. 4,811,075. The '075 patent teaches that this structure approximately doubles the charge in the JFET channel of an HVFET, thereby lowering the R
sp
by about 50%. Because this top layer helps to deplete the extended drain when the extended drain is supporting a high voltage, a high breakdown voltage is maintained despite the increased charge density.
A HVFET in which two JFET channels are arranged in parallel to increase charge and reduce R
sp
is described in U.S. Pat. No. 5,313,082. This structure has several drawbacks. First, proper charge balance among the layers must be maintained in accordance with the RESURF principal discussed above. Secondly, according to the '082 patent the N-well region, the P-type buried region, and the upper N-type region are all diffused from the surface. This makes it very difficult to maintain adequate charge balance among the layers. In addition, the heavily doped p-n junction between the buried layer and drain diffusion region degrades the V
bd
of the device.
Thus, there still exists a need for an improved HVFET and a method of fabricating the same. The HVFET should exhibit a low specific on-state resistance, be easily integrated on the same chip along with low voltage logic devices, achieve the required minimum breakdown voltage in the smallest possible surface area, and be relatively inexpensive to manufacture.
SUMMARY OF THE INVENTION
In one embodiment, the HVFET of the present invention comprises a substrate of a first conductivity type. A first region of a second conductivity type is disposed in the substrate. The first region having a laterally extended portion that forms a lateral boundary with the substrate. A drain diffusion region of the second conductivity type is disposed in the first region and is separated from the lateral boundary by the laterally extended portion. A second region of the first conductivity type is also disposed in the substrate and spaced-apart from the lateral boundary.
The HVFET also includes a source diffusion region of the second conductivity type disposed in the second region. A channel region is formed between the source diffusion region and the lateral boundary. An insulated gate is disposed above the channel region to control current flow therein. A buried region of the first conductivity type is sandwiched within the laterally extended portion of the first region to form a junction field-effect structure in which current flows in the first region both above and below the buried region.


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