High-voltage transistor having a U-shaped gate and method...

Details High-voltage transistor having a U-shaped gate and method... High-voltage transistor having a U-shaped gate and method...

2008-07-15

2008-07-15

Menz, Douglas M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S332000, C257S500000

Reexamination Certificate

active

11003528

ABSTRACT:
According to one exemplary embodiment, a method includes forming first, second, and third shallow trench isolation regions in a substrate, wherein the second shallow trench isolation region is situated between the first and the third shallow trench isolation regions. The second shallow trench isolation region is removed to form a transistor channel trench. A substantially U-shaped gate is formed in the transistor channel trench. According to another embodiment, a transistor includes a substrate, and first and second shallow trench isolation regions in the substrate. A substantially U-shaped gate is formed in the substrate between said first and second shallow trench isolation regions.

REFERENCES:
patent: 5808340 (1998-09-01), Wollesen et al.
patent: 6136675 (2000-10-01), Lee

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