Electronic digital logic circuitry – Tri-state
Reexamination Certificate
1999-09-30
2002-05-14
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Tri-state
C326S083000, C326S080000
Reexamination Certificate
active
06388467
ABSTRACT:
BACKGROUND
1. Technical Field
This invention relates to I/O (input/output) circuitry in a semiconductor device; and, more specifically, it relates to high voltage tolerant I/O circuitry coupled to a sustained tri-state signal line, wherein the voltage on the sustained tri-state signal line may be higher than that of the core circuitry of the integrated circuit.
2. Description of Related Art
Advances in the semiconductor processes used to manufacture today's integrated circuits, in combination with the ever-present need for reduced power consumption, have resulted in semiconductor devices capable of utilizing relatively low operating voltages. For example, operating voltages of 3.3 volts and even 1.8 volts have become common replacements for the traditional 5 volt operating standard. The use of lower operating voltages enables higher frequency operation, as the voltage applied across a semiconductor device is related to its miaximum switching frequency.
In a typical computer system architecture, a processor is coupled to various other devices such as high-speed peripherals, system memory, controllers, etc. via a high-performance bus. An example of such a bus is the PCI Local Bus (PCI bus). The PCI bus is a high-performance bus that provides a processor-.independent data path between the processor and high-speed peripherals. All signals of the PCI bus are bi-directional. The PCI bus is designed to accommodate multiple high-performance peripherals for graphics, motion video, SCSI, LAN, etc. The PCI bus supports two different signaling voltages, 5 volts and 3.3 volts. A given PCd-compatible device may support either or both signaling voltages. Other bus standards or proprietary signaling schemes may have similar voltage requirements.
One known method of supporting both PCI signaling voltages is to use an integrated circuit with a 3.3 volt operating voltage and 5 volt tolerant input/output (I/O) pads. The output pads of such a device drive only 3.3 volts, which satisfies PCI bus specifications. However, this approach may result in 5 volt signals being applied to the I/O pads from an external voltage Source.
Various problems may arise in such a configuration. For example, with certain PCI bus signals, referred to as Sustained Tri-State (STS) signals (e.g., PERR#, SERR#), use of a 5 volt tolerant method to support both 5 volt and 3.3 volt signals may result in the core logic operating voltage of the integrated circuit being less than the logic high voltage level of the STS signal line.
More specifically, the STS signals are required by specification to have a pull-up resistor to either 5 volts or 3.3 volts depending on the specific implantation. When the pull-up resistor is connected to 5 volts, a problem develops if the output driver of the integrated circuit is driving a logic high level (e.g., 3.3 volts). Since the output driver may only drive up 3.3 volts, the 5 volt source coupled to the STS signal may source current through the pull-up resistor to the integrated circuit. The problem is exacerbated with each additional signal that is coupled to the integrated circuit in this manner.
The current sourced to the integrated circuit may cause various problems. For example, the difference between the pull-up voltage at the STS signal line and the operating voltage of the core logic may cause current to be sourced to the core logic, thereby causing a rise in the level of the core operating voltage. The core logic may be damaged when a voltage exceeding its maximum operating voltage is applied. In addition, the unintended flow of current may drain power from the system. Noise and thermal issues may also arise.
Other deficiencies and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art to the present invention as described herein.
SUMMARY OF THE INVENTION
Briefly, an integrated circuit according to the present invention mitigates the deleterious effects of mismatches between the core logic operating voltage and a voltage at an external signal connection point such as a bond pad. The integrated circuit comprises a relatively simple high voltage tolerant output circuit that may be placed in a high impedance state (i.e., tri-stated) when the voltage at a corresponding signal connection point reaches a predetermined voltage reflecting a logic high level.
In one embodiment of the invention, the output circuit is responsive to assertion of a control signal to selectively enter a high impedance state. The control signal is asserted by a control circuit following the detection of a logic high signal of a predetermined duration at the external signal connection point. The predetermined duration may correspond to transmission line delays.
For example, the delay in placing the output circuit in a high impedance state may correspond to the length of time needed to allow transmission line reflections to dissipate to an acceptable level. Disabling the output circuit following such a delay severs the potential current path between the internal operating voltage rails of the integrated circuit and an external voltage source coupled to the signal line via a pull-up device. A corresponding method for controlling an output buffer of an integrated circuit is also disclosed.
The control circuit may receive an indication of the voltage level at the external signal connection point via an input buffer coupled to the external signal point. Alternatively, the control circuit may itself be controlled by core logic of the integrated circuit.
Thus, an output circuit or output driver implemented in accordance with the present invention minimizes the potentially harmful effects of coupling an integrated circuit operating at one voltage to a signal line (such as a sustained tri-state signal line) coupled to a higher voltage.
REFERENCES:
patent: 5570043 (1996-10-01), Churchill
patent: 5635860 (1997-06-01), Westerwick
patent: 5635861 (1997-06-01), Chan et al.
patent: 5825206 (1998-10-01), Krishnamurthy et al.
patent: 5831447 (1998-11-01), Chaw
patent: 6040712 (2000-03-01), Mejia
Mankar Anil
Tennyson Mark R.
Ward Richard A.
Akin Gump Strauss Hauer & Feld L.L.P.
Chang Daniel D.
Conexant Systems Inc.
Tokar Michael
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