High-voltage-tolerant output buffers in low-voltage technology

Details High-voltage-tolerant output buffers in low-voltage technology High-voltage-tolerant output buffers in low-voltage technology

1997-06-19

1999-08-03

Santamauro, Jon

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 58, 326 83, H03K 190185

Patent

active

059330279

ABSTRACT:
An integrated circuit is implemented in a low-voltage technology and has an output driver. The output driver has circuitry adapted to generate an output voltage at an output node (e.g., PAD in FIG. 1) based on an input voltage (e.g., A). Within the output driver, a transistor is configured to limit the drain-to-source voltage drop across another transistor to enable the integrated circuit to tolerate, at its output node, voltages of magnitude up to two times the operating voltage of the integrated circuit. The invention enables low-voltage integrated circuits to be interfaced with other circuitry implemented in a relatively high-voltage technology, without suffering the adverse effects that can otherwise result in the low-voltage circuitry from such interfacing.

REFERENCES:
patent: 4739193 (1988-04-01), Doty, II
patent: 5004936 (1991-04-01), Andresen
patent: 5418476 (1995-05-01), Strauss
patent: 5629634 (1997-05-01), Carl et al.
patent: 5635861 (1997-06-01), Chan et al.
patent: 5748010 (1998-05-01), Haque
patent: 5764077 (1998-06-01), Andresen et al.

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