Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-10-04
2004-10-12
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C326S057000, C326S027000
Reexamination Certificate
active
06803789
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, generally, to an output buffer with a high-impedance state and more particularly, to an output buffer capable of tolerating on its output voltages higher than its supply voltage.
2. Description of the Related Art
In the operation of a system utilizing integrated circuits (IC's) that operate at different power voltages, any IC that is fabricated for use with a given power voltage often interfaces with other IC's in the system in which other IC's operate at a different voltage. More particularly, it often occurs that a 5-V signal on a bus is supplied to the output pad of an IC with a 3.3-V power supply. It is therefore desirable that an output buffer, having a high-impedance state and powered from a supply in the 3.0 to 3.3 volt range, be capable of tolerating, at the output node, logic input signals exceeding the supply voltage, when the output buffer is in the high-impedance state.
A circuit of such a conventional output buffer
100
is shown in FIG.
1
. In
FIG. 1
, IN
102
denotes a signal input, OE (Output Enable)
104
denotes a signal input for enabling the output and an output node
106
, which provides an inverted version of the signal input IN
102
, is connected to an output pad
108
. Signal input
104
(OE, Output Enable) is connected to an active low input of an OR gate
110
and is connected to an input of AND gate
112
. Node DP, the output of the OR gate
110
, is connected to the gate of a p-channel transistor
118
(MP
1
). The p-channel transistor
118
has a channel between its source and drain nodes connected between the voltage supply
120
(V
DD
, typically +3.3 volts) and output node
106
. The substrate of the p-channel transistor is connected to Vdd
120
. Node DN, the output of AND gate
112
, is connected to the gate of an n-channel transistor
126
(MN
1
). The channel of the n-channel transistor
126
is connected between the output node
106
and the reference voltage
128
and the substrate of the n-channel transistor is connected to the reference voltage
128
.
In accordance with the diagram illustrated in
FIG. 1
, the operation of the logic gates
110
,
112
and the transistors MP
1
118
and MN
1
126
is next described. When the OE
104
signal is at logical low (or “0”, disabled), node DP
114
is high and node DN
112
is low, thus turning off transistors MP
1
118
and MN
1
126
and placing the driver in a high-impedance state. When OE
104
is at logical high (or “1”, enabled), the buffer is taken out of the high-impedance state and the output then depends of the state of the IN signal. If IN
102
is at logical low (or “0”), DP
114
and DN
122
are both low (or “0”) and transistor MP
1
118
is on while MN
1
126
is off, causing the output node
106
to be pulled close to the supply voltage Vdd.
If IN
102
is at logical high (or “1”) while OE
104
is at logical high (or “1”, enabled), DP
114
and DN
122
are at both high (or “1”) and transistor MP
1
118
is turned off while MN
1
126
is turned on, causing the output node
106
to be pulled close to the reference voltage (Gnd)
128
.
The foregoing output buffer operates under the condition that a signal applied to the output node cannot substantially exceed the voltage of the supply voltage
120
(typically about +3.3 volt). If a signal applied to the output node does exceed the supply voltage, the channel end of p-channel transistor
118
connected to the output
106
has a voltage that is more positive than its gate voltage, which is close to the supply voltage, causing its channel to conduct from the output
106
back to the supply node
120
. The higher voltage (such as 5 V) at the output forward biases the body diode of the p-channel transistor causing leakage currents and degradation of the buffer gate-oxide of the transistor, leading to reduced reliability.
The prior art buffer circuit of
FIG. 2
attempts to overcome this problem. Referring to
FIG. 2
, the output buffer
200
includes a pair of p-channel pull-up transistors MP
1
, MP
2
, an n-channel pull-down transistor MN
1
, an enable transistor MN
3
, an inhibit transistor MP
4
, an OR and an AND gate.
The p-channel pull-up transistors MP
1
, MP
3
have their channels connected in series between the voltage supply node Vdd and the output node
206
. In particular, the transistor MP
1
218
has its source and substrate connected to the voltage supply V
DD
220
(typically at +3.3 volts) and its drain connected to node A
222
. The transistor MP
3
242
has its channel connected between the node A
222
and the output node
206
. The transistor MP
3
242
has its substrate coupled to the output node
206
. The channel of the transistor MN
1
228
is connected between the output node
206
and the reference voltage
244
. The transistor MN
3
238
has its channel connected between the gate
240
of transistor MP
3
242
and the reference potential
244
. The channel of the transistor MP
4
236
is connected between the gate
240
of transistor MP
3
242
and the output node
206
, which also connects to the substrate of MP
4
.
The output of the AND gate
212
is connected to the gate of a pull-down transistor MN
1
228
and the output of the OR gate
210
, is connected to the gate
216
of a pull-up transistor MP
1
218
. The OE
204
signal input is connected to the gates
232
,
234
of transistors MP
4
236
and MN
3
238
. The OE
204
signal input also is connected to an active low input of an OR gate
210
and to an input of AND gate
212
. The IN signal is connected to an active high input of the OR gate
210
and to the other input of the AND gate
212
.
Compared to the output buffer
100
shown in
FIG. 1
, the output buffer
200
in
FIG. 2
is includes the inhibiting circuit
230
, which includes MP
3
, MP
4
, and MN
3
. When the output enable signal OE
204
is a logical low (or “0”), the transistor MN
3
238
is off and the transistor MP
4
236
is in a low-impedance state connecting the gate and the source of the transistor MP
3
240
. This forces transistor MP
3
240
into a high-impedance state because MP
3
has no source-to-gate voltage. If a voltage, such as 5 V, greater than the supply voltage Vdd is applied to node
206
, a high impedance is presented to the output node
206
and current flow from the output node
206
back to the power supply
220
is inhibited for any signal exceeding the power supply voltage by about 2 to 3 volts. When the signal at OE
204
input is at logical high (or “1”), the transistor MP
4
236
is non-conducting and the transistor MN
3
238
is on. The drain of the transistor MN
3
234
pulls down the gate of the transistor MP
3
242
, to a voltage near the reference voltage, thus turning on transistor MP
3
. Transistors MP
1
216
and MN
1
226
therefore, operate as in the conventional circuit, driving the output node
206
and presenting a low impedance.
However, in the output buffer
200
of
FIG. 2
, the transistors MP
1
218
and MP
3
240
are formed in different n-wells, leading to problems due to more occupied chip size and gate-oxide integrity.
Therefore, there is a need for an improved output buffer that can withstand signal from 0 to 5 V applied to its output, and overcome the problems related to gate-oxide integrity without increasing the chip size.
BRIEF SUMMARY OF THE INVENTION
A driver in accordance with the present invention includes (i) pull-up means, responsive to an output enable signal and an input data signal, for providing a low or high impedance path between a first supply voltage and an output node. The low impedance path is present when the output enable signal and the input data signal are both a logic high, the high impedance path is present when the either the output enable signal or the input data signal is a logic low, and the pull-up means is connected to a substrate bias voltage that is the greater of the output voltage when the pull-up means has a high-impedance path and the first supply voltage. The present invention further includes (ii) pull-down mea
Yang Paul H. Ou
Yu Ta-Lee
Le Don
Semiconductor Manufacturing International Corporation
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