High voltage-tolerant low voltage input/output cell

Details High voltage-tolerant low voltage input/output cell High voltage-tolerant low voltage input/output cell

1996-06-13

1999-02-23

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 83, 326 81, H03K 190175, H03K 19094

Patent

active

058748385

ABSTRACT:
An improved I/O cell is disclosed which includes a combined p-channel and n-channel transistor pullup configuration. In particular, such combination is connected in series between the chip operating voltage V.sub.cc, and the I/O cell output pad. The n-channel transistor is biased substantially continuously on its gate terminal with a pumped voltage from a charge pump, which permits it to pass voltages up to and including V.sub.cc. The p-channel transistor operates in its normal fashion, controllable via a pullup select signal applied to its gate terminal to pull the pad high. During normal operation, the n-channel transistor is always ON, thus reducing the substantial dynamic current drawn from the charge pump. The voltage appearing on the pad is fed back to a second n-channel transistor. When the voltage on the pad exceeds V.sub.cc for example, a 5 volt signal when V.sub.cc is 3.3 volts), the second n-channel transistor switches the gate of the first n-channel transistor to a reference signal, which is a diode drop below V.sub.cc. The first n-channel transistor, in response thereto, shuts-off, thus protecting the p-channel pullup transistor from the excessive voltages appearing on the pad.

REFERENCES:
patent: 5057715 (1991-10-01), Larsen et aL.
patent: 5150186 (1992-09-01), Pinney et al.
patent: 5319259 (1994-06-01), Merrill
patent: 5565794 (1996-10-01), Porter

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