Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-03-03
2001-12-25
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S541000, C327S543000, C326S081000, C365S189090
Reexamination Certificate
active
06333663
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 99-7117, filed on Mar. 4, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a high-voltage tolerant interface circuit.
Through the use of a deep-submicron line width in the processing of semiconductor memory devices, a required power supply voltage as high as 3.3V has gradually been decreased to a lower voltage of approximately 2.5V. Most semiconductor memory devices include a plurality of input/output buffers, which operate to buffer data input with such a low power voltage.
Although the power supply voltage level applied to the input/output buffers has decreased, an external high-voltage signal of 5V can also be input to these input/output buffers. As a result, the input/output buffers must have the ability to tolerate a high-voltage of 5V for interfacing with an external 5V-input signal. These 5V-tolerant semiconductor memory devices are commonly used in low-power consumption devices and portable device applications.
However, conventional 5V-tolerant input/output buffers are effective only when an external power voltage is input. In order to protect metal oxide semiconductor (MOS) transistors included in the input/output buffers, it is necessary for the device to have the ability to tolerate voltage levels as high as 5V, even when no external power supply voltage is applied to a semiconductor memory device.
In general, the gates of NMOS and PMOS transistors of the input/output buffers operating with a low power supply voltage are formed having a thin dielectric film, e.g., a thin oxide film, with a low tolerant voltage level. In such a device, if a 5V-signal is applied to the drain or source of the NMOS and PMOS transistors, without the power supply voltage being applied to the gates of the NMOS and PMOS transistor, the gate-source voltage or the gate-drain voltage of the NMOS and PMOS transistors may increase and exceed the tolerable voltage limit of the gates of the NMOS and PMOS transistors. If this happens, the gates of the NMOS and PMOS transistors may b e broken, resulting in improper operation of the device.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a high-voltage tolerant interface circuit that is able to tolerate an external high-voltage of 5V or more even when no power supply voltage is applied.
Another object of the present invention is to provide a semiconductor memory device having a high-voltage tolerant interface circuit that is able to tolerate an external high-voltage of 5V or more unaffected regardless of application of the power supply voltage.
To achieve the first object of the present invention, a high-voltage tolerant interface circuit is provided. This circuit comprises a terminal; a first buffer including a plurality of MOS transistors with first electrodes connected to the terminal, for converting the voltage level of an input signal and transferring the converted voltage to the terminal; a second buffer including at least one MOS transistor with a first electrode connected to the terminal, for converting the voltage level of the signal transferred from the terminal; and a voltage control unit connected to the terminal for providing an internal supply voltage to the MOS transistors of the first and second buffers, wherein the internal power supply voltage is equal to an external power supply voltage when the external power supply voltage is applied to the high-voltage tolerant interface circuit, and wherein the internal power supply voltage is equal to a predetermined voltage level when the external power supply voltage is not applied to the high-voltage tolerant interface circuit and a high-voltage greater than the external power supply voltage is input to the terminal. The predetermined voltage level is preferably higher than 2 volts.
The internal power supply voltage is preferably set to the predetermined voltage level by pulling down the high-voltage input at the terminal to the predetermined voltage level. The voltage control unit preferably comprises a voltage pull-down circuit for pulling down the high-voltage to the predetermined voltage level. The voltage pull-down circuit preferably comprises a plurality of diodes arranged in series and connected with the terminal.
The voltage control unit preferably comprises: a switching control unit for receiving a first control signal and outputting second and third control signals, the first control signal instructing the switching control unit to enable the second control signal when the external power supply voltage is applied, and the first control signal instructing the switching control unit to enable the third control signal when the high-voltage is input to the terminal without the application of the external power supply signal; a first switch for passing the external power supply voltage as the internal power supply voltage in response to the enabling of the second control signal; and a second switch for passing the predetermined voltage pulled down by the voltage pull-down circuit as the internal power supply voltage in response to the enabling of the third control signal, wherein the voltage control unit outputs the internal power supply voltage at a node located between the first and second switches. The voltage control unit may further comprise a voltage discharge circuit for discharging a portion of the high-voltage to reduce it to the predetermined voltage level.
The high-voltage may be a voltage associated with a transistor-transistor logic (TTL) level.
“To achieve the second object of the present invention, a semiconductor memory device having an internal circuit is provided. This semiconductor memory device comprises a pad to and from which an external signal is input and output; an output buffer having a plurality of MOS transistors with first electrodes connected to the pad, for changing a voltage level of data output from the internal circuit, and transferring the converted voltage to the pad; an input buffer having at least one MOS transistor with a first electrode connected to the pad, for converting the voltage level of data input to the pad from an outside source, and transferring the converted voltage to the internal circuit; and a voltage control unit connected to the pad, for providing an internal supply voltage to the MOS transistors of the first and second buffers, wherein the internal power supply voltage is equal to an external power supply voltage when the external power supply voltage is applied to the high-voltage tolerant interface circuit, and wherein the internal power supply voltage is equal to a predetermined voltage level when the external power supply voltage is not applied to the high-voltage tolerant interface circuit and a high-voltage of magnitude greater than the external power supply voltage is input to the pad.”
“The internal power supply voltage is preferably set to the predetermined voltage level by pulling down the high-voltage input at the pad to the predetermined voltage level. The voltage control unit preferably comprises a voltage pull-down circuit for pulling down the high-voltage.”
The voltage control unit may also comprise: a switching control unit for receiving a first control signal and outputting second and third control signals, the first control signal instructing the switching control unit to enable the second control signal when the external power supply voltage is applied, and the first control signal instructing the switching control unit to enable the third control signal when the high-voltage is input to the terminal without the application of the external power supply signal; a first switch for passing the external power supply voltage in response to the enabling of the second control signal; and a second switch for passing the predetermined voltage in response to the enabling of the third control signal, wherein the voltag
Callahan Timothy P.
Englund Terry L.
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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