High voltage tolerance output stage

Details High voltage tolerance output stage High voltage tolerance output stage

2007-10-09

2007-10-09

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000, C257S370000, C257S371000

Reexamination Certificate

active

11162001

ABSTRACT:
An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

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