Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-11-28
2003-10-28
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S017000, C326S031000, C326S087000, C326S081000, C327S333000, C327S065000, C365S189110
Reexamination Certificate
active
06639427
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a high voltage switching device. The high voltage switching device may be applied to non-volatile memories, such as a FAMOS type non-volatile memory as well as EPROM, EEPROM and Flash EPROM-type non-volatile memories.
The above mentioned memories include connection lines connected to rows of memory cells. A high voltage or a low voltage must be provided to these rows of memory cells. The present invention intends to accelerates the discharge rate of the connection lines from the high voltage to the low voltage. More particularly, the invention is concerned with output lines controlled by the switching device that are capacitive and are capable of conducting current.
BACKGROUND OF THE INVENTION
In an exemplary application to a FAMOS type non-volatile memory, connection lines will typically be connected to rows of memory cells that contact the sources of FAMOS transistors within each memory cell. In this type of application, the switching device, in addition to the usual translator type switch, must have an additional switching transistor. First, the switching transistor initially helps the switch to discharge the output line(s) from the high voltage level to a low voltage level, which is typically the logic supply voltage Vcc. Second, the switching transistor must hold the low voltage level on these lines. Thus, in the latter case, this switching transistor provides the current needed to hold the voltage level on the line.
In the exemplary application to the rows of the FAMOS memory cells, the rows must be held at the logic supply voltage level Vcc during the read operation. In an exemplary application to Flash EPROMs, these output lines will be the rows connected to the control gates of the floating gate transistors. The switching transistor then holds these lines at the logic supply voltage level during a read operation, and at a high voltage level during a programming operation. In an application of this kind, a device for drawing the voltage to zero must be provided to draw the unselected rows to zero.
FIG. 1
shows a prior art MOS technology switching device applied to a row of FAMOS type memory cells. The device is made, in the example, with N-type and P-type MOS transistors. This switching device conventionally, as explained above, comprises a translator type switch and an additional switching transistor.
The switching device has two switching arms B
1
and B
2
. The two switching arms have a similar structure. The switching arm B
1
has a load transistor M
10
connected to the high voltage HV, a switching transistor M
13
connected to ground Gnd and receiving at its gate a logic control signal CTRL, and a cascode stage connected between these two transistors. In the example, the cascode stage has two cascode transistors M
11
and M
12
. In practice, it has at least one of them. The connection point N
10
between the load transistor M
10
and the cascode transistor M
11
of an arm is applied as a signal to activate the load transistor of the other arm.
Similarly, the arm B
2
comprises a load transistor M
20
connected to the high voltage HV, a switching transistor M
23
connected to ground Gnd and receiving at its gate the reverse control signal CTRL, and a cascode stage connected between these two transistors M
20
and M
23
. In the example, the cascode stage has two cascode transistors M
21
and M
22
, biased by reference voltages V
REFP
and V
REFN
given by a generation circuit that is not shown. The transistors M
20
and M
21
are P-type MOS transistors, and the MOS transistors M
22
and M
23
are N-type MOS transistors. The connection point N
20
between the load transistor M
20
and the cascode transistor M
21
of an arm is applied as a signal to activate the load transistor M
10
of the other arm.
In the example, it is the node N
10
of the first arm B
1
that gives the output signal of the switch. This node N
10
is therefore connected to an output line L
1
, which is a capacitive line. In a well known way, and without being necessary to provide a detailed description on the operation of the switch, the node N
10
has a level corresponding to the high voltage HV when the control signal CTRL is at the logic level
1
and while the load transistor M
13
is off. The node N
10
has a logic supply voltage level Vcc when the control signal CTRL is at the logic level
0
and while the load transistor M
13
is off.
In the example, the output line L
1
controlled by the switch corresponds to a row of FAMOS cells, which contacts all the sources of the FAMOS transistor in the row of cells.
FIG. 1
shows only one of these cells, which comprises a FAMOS transistor and an associated selection transistor. The cell sources are connected to a corresponding bit line through which the cell state is read while the row is taken to the logic supply voltage level Vcc. Furthermore, cell programming is obtained while the associated row is taken to the high voltage level
1
.
In the read mode, if the cell is programmed, the row potential tends to drop. It is therefore necessary to plan for the switching device to maintain the row at the read potential, namely the logic supply voltage level Vcc. This function is fulfilled by the additional switching transistor M
30
, connected between the logic supply voltage level Vcc and the output line L
1
.
Furthermore, when the line L
1
is at the high voltage and the switch trips into the other state, this switching transistor provides knowledge that the node N
10
has gone to the logic supply voltage level Vcc. This provides the discharge current of the capacitive line L
1
, and brings this line from the high voltage level to the lower logic supply voltage level Vcc. In practice, this transistor is controlled by the connection node between the two cascode transistors of the arm providing the output signal of the switch. In the example, it is the node N
11
of the arm B
1
.
If the switch comprises only one cascode transistor per arm, the connection node used is the one between the single cascode transistor and the switching transistor of the arm giving the output signal. When the node N
10
is at the high voltage level, the node N
11
is also at the high voltage level HV. When the node N
10
is at the logic supply voltage level Vcc, the node N
11
is drawn to zero.
The additional switching transistor M
30
is subjected to repeated electrical stresses in the device. If it is assumed that the node N
10
and therefore the output line L
1
are at the high voltage level HV, the gate of the switching transistor M
30
connected to the node N
11
is also at the high voltage level. This turns the switching transistor M
30
off. If the switch trips, the node N
10
goes to Vcc. The switching transistor M
30
absorbs the discharge current that takes the capacitive line L
1
from the high voltage level HV to the low voltage level Vcc.
However, this discharge is slow due to the capacitance of the line L
1
. The node N
11
of the switch swiftly goes to a zero voltage level. Thus, there is a very high potential difference between the gate and the electrode of the transistor M
30
connected to the line L
1
during a part of the discharge time of the line L
1
.
SUMMARY OF THE INVENTION
An object of the invention is to resolve the problem of electrical stresses on the switching transistor M
30
. The invention is based upon keeping the potential difference between the gate of the transistor M
30
and the output line constant. In a high voltage level switching device with a translator type switch, a low voltage level switching transistor is provided. This transistor is activated by an output signal of the switch. This output signal is controlled by a circuit used to set up a control loop between the drop in the gate voltage level of the switching transistor, and the drop in the voltage level of the output line controlled by the switch.
The invention therefore relates to a MOS technology switching device comprising a translator type switch to switch a high voltage level to at least one capacitive type output line
Dray Cyrille
Thomas Sigrid
Chang Daniel
Jorgenson Lisa K.
STMicroelectronics SA
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