High-voltage semiconductor device

Details High-voltage semiconductor device High-voltage semiconductor device

2000-12-15

2004-06-15

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S298000, C257S315000, C257S316000, C257S319000, C257S320000, C257S326000, C257S296000, C257S300000, C257S401000, C257S335000, C257S488000, C257S489000, C257S490000, C365S185010, C365S185070

Reexamination Certificate

active

06750506

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device with a high breakdown voltage (which will be herein called a “high-voltage semiconductor device”).
Hereinafter, a known high-voltage semiconductor device will be described with reference to FIG.
14
.
FIG. 14
is a perspective view schematically illustrating a cross-sectional structure for an insulated-gate transistor.
As shown in
FIG. 14
, the transistor includes a p-type semiconductor substrate
1
. In the substrate, n-type lightly doped semiconductor region
2
, p-type doped isolating region
3
, p-type doped body region
4
and n-type heavily doped source/drain regions
5
and
6
have been defined. These regions
2
,
3
,
4
,
5
and
6
will be herein called “semiconductor region”, “isolating region”, “body region” and “source/drain regions”, respectively, for the sake of simplicity. The isolating region
3
is provided to electrically isolate an adjacent pair of devices from each other. The body region
4
is defined in the semiconductor region
2
, the source region
5
is defined in the body region
4
and the drain region
6
is defined in the semiconductor region
2
.
An oxide film with non-uniform thicknesses has been deposited over the semiconductor region
2
. A thinner portion of the oxide film is used as a gate oxide
7
, while a thicker portion thereof is identified by the reference numeral
8
. The oxide film
7
,
8
is covered with an interlevel dielectric film
9
. Electrodes
10
b
,
11
b
and
12
b
of polysilicon have also been formed over the oxide film
7
,
8
. Specifically, the electrode
10
b
functions as gate electrode, the electrode
11
b
is an electrically floating plate electrode, and the electrode
12
b
is a plate electrode connected to a drain electrode
15
. It should be noted that parts of the interlevel dielectric film
9
, which actually covers these electrodes
10
b
,
11
b
and
12
b
, are not illustrated in
FIG. 14
to make the structure of this transistor easily understandable.
As also shown in
FIG. 14
, five other metal electrodes
13
,
14
,
15
,
16
and
17
are also provided. Specifically, the electrode
13
is connected to the body region
4
and will be herein called a “body electrodes”. The electrode
14
makes electrical contact with the source region
5
and will be herein called a “source electrode”. The electrodes
16
and
17
are electrically floating electrodes. And the electrode
15
makes electrical contact with the drain region
6
and will be herein called a “drain electrode”. Although not illustrated in
FIG. 14
, a protective coating has actually been deposited over the electrodes
13
through
17
and interlevel dielectric film
9
, and the chip including these components is entirely covered with a plastic encapsulant.
In the structure illustrated in
FIG. 14
, a predetermined part of the n-type semiconductor region
2
is surrounded with the p-type isolating region
3
in the p-type semiconductor substrate
1
. The drain region
6
is located approximately at the center of that part of the semiconductor region
2
. Also, the p-type body region
4
has been defined along the isolating region
3
, which defines the periphery of that part the semiconductor region
2
. And the n-type source region
5
has been defined inside the body region
4
.
In the insulated-gate transistor shown in
FIG. 14
, a ground potential GND is applied to the source electrode
14
, body electrode
13
, substrate
1
and isolating region
3
, a positive high potential is applied to the drain electrode
15
and a control voltage is applied to the gate electrode
10
b
. The plate electrodes
11
b
and
12
b
, connected to the drain region
6
, are a type of field plates. These plate electrodes
12
b
and
11
b
are capacitively coupled to the floating metal electrodes
16
and
17
, respectively, through the interlevel dielectric film
9
over the electrodes
12
b
and
11
b
. In this manner, the potential difference between the drain and gate electrodes
15
and
10
b
is divided by the capacitive divider so that potential is not concentrated at a particular surface area in the semiconductor region
2
.
Next, it will be briefly described how the insulated-gate transistor shown in
FIG. 14
operates. When a positive voltage, equal to or higher than its threshold voltage, is applied as a control voltage to the gate electrode
10
b
, part of the p-type body region
4
, located near the surface and under the gate electrode
10
b
, changes into the opposite type, or n-type. As a result, a so-called “channel region” is created to turn the insulated-gate transistor ON. In this case, a current flows from the drain region
6
toward the source region
5
by way of the semiconductor region
2
and channel region near the surface of the body region
4
. Conversely, if the voltage applied to the gate electrode
10
b
is reduced to less than its threshold voltage, then the channel region shrinks its size considerably to turn the insulated-gate transistor OFF. As used herein, the “breakdown voltage” of a transistor means a voltage below which the transistor is kept OFF. Thus, a “high-voltage transistor” can be kept OFF even when a high bias voltage (e.g., 100 V or more) is applied thereto.
FIG. 15
illustrates parasitic capacitances formed in the high-voltage semiconductor device shown in FIG.
14
.
FIG. 16
illustrates potential profiles created when a high voltage (e.g., 600 V) is applied to the device shown in FIG.
14
. In
FIG. 16
, each dashed line indicates an equipotential line.
As shown in
FIG. 15
, a parasitic capacitance C
1
exists between the gate and floating metal electrodes
10
b
and
17
. A parasitic capacitance C
2
exists between the floating metal and plate electrodes
17
and
11
b
. A parasitic capacitance C
3
exists between the plate and floating metal electrodes
11
b
and
16
. And a parasitic capacitance C
4
exists between the floating metal electrode
16
and plate electrode
12
b
connected to the drain potential. A serial circuit, formed by these parasitic capacitances C
1
through C
4
, divides the potential difference, thereby regulating the potential at the plate electrode
11
b
and creating appropriate potential profiles in the semiconductor region
2
. It should be noted that parasitic capacitances C
5
and C
6
, formed between the metal electrodes
16
and
17
and plastic encapsulant
19
shown in
FIG. 15
, are normally considered non-existent as will be described later.
Referring to
FIG. 16
, potential profiles at room temperature in the known high-voltage semiconductor device are schematically illustrated. The present inventors confirmed that the potential profiles illustrated in FIG.
16
and results of simulations we carried out showed similar tendencies.
The profiles illustrated in
FIG. 16
were obtained where a ground potential of 0 V was applied to the substrate
1
, isolating region
3
, body region
4
, source region
5
and gate electrode
10
a
and a voltage of 600 V was applied to the drain region
6
. The control voltage applied to the gate electrode
10
b
was actually around 10 V. However, since this value is much lower than 600 V applied to the drain electrode
15
, the same profiles are obtained whether the control voltage is 0 V or 10 V. Thus, the control voltage is regarded as 0 V for convenience sake.
As shown in
FIG. 16
, when the same high potential as that applied to the drain region
6
, i.e., 600 V, is applied to the plate electrode
12
b
, an intermediate potential between 600 V and 0 V will be applied to the plate electrode
11
b
. Accordingly, the equipotential lines, representing the potential profiles in the semiconductor region
2
, extend almost vertically to the surface of the semiconductor region
2
, and are distributed almost equidistantly from each other. As a result, the concentration of electric field in the semiconductor region
2
can be reduced and the breakdown voltage of the transistor can be kept sufficiently high.
However, if the device is operated at an elevated ambient

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