High voltage random-access memory cell incorporation level shift

Details High voltage random-access memory cell incorporation level shift High voltage random-access memory cell incorporation level shift

1993-08-23

1994-11-22

La Roche, Eugene R.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 36518911, G11C 1140

Patent

active

053674820

ABSTRACT:
A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled. The gates of the first and third N-channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-channel MOS transistors are formed in an n-well biased at power supply voltage V.sub.HS. A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

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