Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
1999-02-19
2001-10-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000, C326S120000
Reexamination Certificate
active
06300796
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of high voltage PMOS circuits. Specifically, the present invention relates to level shifter circuits having complimentary low voltage inputs and complementary high voltage outputs.
2. Discussion of the Related Art
Due to device limitations, conventional level shifter circuits for high voltage operations are prone to breaking down when high voltage is present. Specifically, MOSFET parameters which may limit conventional circuits ability to handle high voltage are the oxide breakdown voltage, the punch-through breakdown voltage, and the junction breakdown voltage.
The oxide breakdown voltage is the gate to source or the gate to drain voltage at which the gate oxide ruptures. For example, the gate oxide breakdown voltage of a modern device with gate oxide thicknesses of about 150 Angstroms is approximately 12 volts. However, with sufficient gate oxide thicknesses, destructive gate oxide ruptures are eliminated.
The punch-through breakdown voltage is the drain to source or source to drain voltage at which the drain current abruptly increases. Continued operation in this condition may generate enough heat to damage the MOSFET. The punch-through breakdown can be prevented by constructing the gate length of the MOSFET longer then the drain to source or source to drain depletion length.
Even when the parameters of a MOSFET are adequate to overcome oxide and punch-through breakdowns, a junction breakdown can still occur. The junction breakdown voltage is the drain or source to substrate voltage that is the level of reverse bias between the drain or source and the substrate at which the reverse-biased diode junction used for electrical isolation of the drain or source breaks down due to avalanching or Zener behavior. For a typical modern device parameters, the junction breakdown voltage for a standard transistor having a 10 volt gate to substrate voltage is about 10 volts. At this gate voltage level, as the gate voltage rises, the junction breakdown voltage increases approximately linearly with the gate voltage by a factor of about 1.0 times the gate to substrate voltage.
As is apparent from the above discussion, a need exists for a high voltage PMOS level shifter which allows switching to occur during high voltage operation without violating any breakdown limitations, especially the junction breakdown limitation.
SUMMARY OF THE INVENTION
Conventional high voltage level shifters are not able to switch states while operating under the high voltage conditions because junction breakdown constraint would be violated under these circumstances. The oxide breakdown voltage constraint and the punch-through voltage constraint also limited the feasible high voltage circuit designs. Thus, an object of the present invention is to provide a high voltage level shifter which does not violate the junction breakdown, oxide breakdown, and the punch-through breakdown constraints
According to the present invention, one or more complementary pairs of transistors connected together in series separate the output terminal from the input terminal. Preferably, each pair has a standard high voltage enhancement PMOS with limited breakdown characteristics such as less than 17 volts, and a high voltage depletion PMOS with high voltage breakdowns such as greater than 17 volts.
In the preferred embodiments, when connected in series, the high voltage depletion PMOS protects the standard high voltage enhancement PMOS from breakdowns at high voltages, for example, that can range approximately between 16 and 20 volts. Typically transistors that can withstand high voltages have slower switching speed than transistors that cannot withstand high voltages.
With respect to the electrical connections of the series transistor pair in the preferred embodiments, the source of the high voltage depletion PMOS and the drain of the standard high voltage enhancement PMOS are connected together. The substrates of both transistors and the source of the standard high voltage enhancement PMOS are tied to a constant first voltage source preferably approximately between 16 and 20 volts. The gates of both transistors are connected to a second voltage source that preferably is selectively about 0 volt or about between 16 and 20 volts for turning on and for turning off both transistors respectively. The drain of the high voltage depletion PMOS is tied to a third voltage source that preferably is selectively about 0 volt or about between 16 and 20 volts when both transistors are off and when both transistors are on respectively.
One or more of the inventive series transistor pairs can be used within various circuitry embodiments to shift a low voltage preferably approximately between 0 and 5 volts to a high voltage preferably approximately between 16 and 20 volts without suffering from any high voltage breakdowns.
REFERENCES:
patent: 4161663 (1979-07-01), Martinez
patent: 4663701 (1987-05-01), Stotts
patent: 4831284 (1989-05-01), Anderson et al.
patent: 4890146 (1989-12-01), Williams et al.
patent: 4920284 (1990-04-01), Denda
patent: 5243236 (1993-09-01), Mcdaniel
patent: 5406142 (1995-04-01), Nakama et al.
patent: 5457420 (1995-10-01), Asada
patent: 5669684 (1997-09-01), Agan
patent: 5684415 (1997-11-01), McManus
patent: 5698993 (1997-12-01), Chow
patent: 5736774 (1998-04-01), Fujihira
patent: 5821800 (1998-10-01), Le et al.
Manos, II Peter D.
Troutman Bruce Lee
Skjerven Morrill & MacPherson LLP
Tokar Michael
Tran Anh
Zilog Inc.
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