High voltage planar edge termination structure and method of mak

Details High voltage planar edge termination structure and method of mak High voltage planar edge termination structure and method of mak

1994-07-05

1996-01-23

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

With inversion-preventing shield electrode

257654, H01L 2358

Patent

active

054867185

ABSTRACT:
A semiconductor structure having an edge termination feature wherein a first doped region and a second doped region are selectively formed in a semiconductor layer. The second doped region is coupled with the first doped region and has an impurity concentration less than that of the first doped region. An insulating layer is disposed over the semiconductor layer and over at least a portion of the second doped region. A conductive layer, having a coil-shaped configuration, is disposed over the insulating layer and is coupled to the semiconductor layer.

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patent: 5113237 (1992-05-01), Stengl
patent: 5266831 (1993-11-01), Phipps et al.
Solid State Electronics, 1972, vol. 15, pp. 653-657, "Enhancement of Breakdown Properties of Overlay Annular Diodes By Field Shaping Resistive Films", L. E. Clark et al.
IEEE Electron Device Letters, vol. E1 L-6, No. 9, Sep. 1985, "A Proposed Planar Junction Structure With Near-Ideal Breakdown Characteristics", S. Ahmad et al.
Proceedings of the IEEE, vol. 55, No. 8, Aug. 1967, "High-Voltage Planar P-N Junctions", Y. C. Kao et al.
Proceedings of 1990 International Symposium on Power Semiconductors Devices and ICs, Tokyo, "Novel Planar Junction Termination Technique For High Voltage Power Devices", T. Stockmeier et al., pp. 236-239.
Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Tokyo, "High Voltage (4KV) Emitter Short Type Diode (ESD)", Mitsuhiko Kitagawa et al., pp. 60-65.

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