Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – Field relief electrode
Reexamination Certificate
2002-09-26
2004-01-13
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
Field relief electrode
C257S508000, C257S520000
Reexamination Certificate
active
06677657
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the manufacturing of discrete components in silicon wafers. More specifically, the present invention relates to the periphery of high-voltage components in silicon-on-insulator wafers.
2. Discussion of the Related Art
FIGS. 1A
to
1
D illustrate, in a simplified partial cross-section view, different steps of the forming of a high-voltage discrete component in a silicon-on-insulator (SOI) semiconductor substrate.
As illustrated in
FIG. 1A
, the process starts from a single-crystal silicon substrate
1
of a first conductivity type, for example, N. Substrate
1
includes a heavily-doped buried layer
2
of the same type N, which rests on an insulating layer
3
, typically silicon oxide, supported by a lower single-crystal silicon substrate
4
of the second conductivity type, for example, P. This assembly is typically formed by pasting two silicon wafers separated by an insulator and by leveling one of the wafers. As illustrated to the right of the drawing, one or several elements of the component to be formed have for example been formed in substrate
1
, such as a lightly-doped P-type well
5
. The implantation of well
5
is followed by the forming, on the entire exposed surface of substrate
1
, of a protection layer
6
, generally silicon oxide.
As illustrated in
FIG. 1B
, the periphery of the discrete component is defined by a trench
7
joining insulating layer
3
. Trench
7
is intended to separate, that is, to isolate, two neighboring components. As an example, trench
7
is considered to separate the considered component from an unused portion of substrate
1
(to the left of the drawing) separated from another component (not shown) by another trench (not shown). The opening of trench
7
is followed by a doping of its edges. A heavily-doped N-type region
8
in contact with buried layer
2
via a vertical region
9
along the wall of trench
7
is thus formed at the surface of substrate
1
, at the component periphery. An insulating layer
10
, typically thermal silicon oxide, is then formed on the walls of trench
7
.
Then, as illustrated in
FIG. 1C
, a material is deposited to completely fill trench
7
. The material is preferably an insulating or amorphous material, generally undoped polysilicon. The material then is removed outside of the trench by chem-mech polishing (CMP). A peripheral wall
12
separated from peripheral region
8
and vertical region
9
and from buried layer
2
by insulating layer
10
has thus been formed around the portion of substrate
1
in which the component is formed.
As illustrated in
FIG. 1D
, the structure is then coated with a layer
13
of a dielectric. The method carries on with the forming in and/or around well
5
of specifically doped regions, then of contacts between metal tracks formed on dielectric
13
and such specific regions and/or well
5
and/or substrate
1
and/or peripheral region
8
before passivating the assembly. The component thus formed may be any type of high-voltage component such as a thyristor, an NPN or PNP type bipolar transistor, or a diode. As a non-limiting example,
FIG. 1D
illustrates a heavily-doped P-type region
14
formed at the surface of well
5
and put in contact by a via
15
with a superposed metal track
16
.
A disadvantage of this type of structure is the component breakdown voltage problems. Indeed, in the component operation, a situation may occur in which substrate
1
, buried layer
2
, vertical contact
9
, and peripheral region
8
must altogether be maintained at a high voltage level while superposed metallization
16
is at a low biasing level. It is desired to be able to have a high potential difference between the high and low levels, for example, on the order of 600 volts. For this purpose, the component is designed with a substrate
1
having a theoretically appropriate thickness, for example, on the order of 60 &mgr;m. Further, it is known that, to reach such high voltage levels, it is desirable to increase the thickness of insulator
6
-
13
between metal track
16
and substrate
1
and/or to select insulators with a low dielectric permittivity.
However, such an overthickness is incompatible with usual manufacturing methods and poses many problems, especially of mechanical stress on underlying substrate
1
, of forming of the openings necessary to the doping of specific regions
14
, or of forming of vias
15
. Materials with a low permittivity, such as polyimide, also pose manufacturing problems and impose specific precautions of use, especially of etching.
To overcome these disadvantages and be able to use a standard insulator having a standard thickness, it has been provided, as illustrated in
FIG. 2
, to form a metal field plate
18
in contact with peripheral region
8
and extending beyond the border between this region and substrate
1
. However, the forming of such a plate imposes, from the forming of wall
12
described in relation with
FIG. 1C
, opening layer
6
and implementing specific steps of deposition and etching of a metal layer according to the pattern of plate
18
. To enable subsequent etching of the metal layer without damaging wall
12
, the deposition thereof is preceded by the deposition of an etch stop layer, not shown. Such a use of an additional metal level thus complicates the manufacturing process.
SUMMARY OF THE INVENTION
The present invention aims at providing discrete high-voltage components which overcome the preceding disadvantages.
The present invention more specifically aims at providing a structure of a field plate SOI-type component which is easy to manufacture.
To achieve these and other objects, the present invention provides a method for forming a component in a portion of a semiconductor substrate on insulator delimited by a lateral wall separated by an insulating layer from a peripheral region internal to said portion and heavily doped of a same first conductivity type as said substrate. A conductive plate is formed at the same time as said wall, on a layer of protection of the substrate surface, in electric contact with the peripheral region, said plate extending above said peripheral region towards the inside of said portion with respect to the wall beyond the location above the limit between the peripheral region and the substrate.
According to an embodiment of the present invention, the forming of the wall and of the plate in contact with the peripheral region is performed to simultaneously form an additional plate continuing the wall, independent from the plate in contact with the peripheral region and having its upper surface coplanar to that of the plate in contact with the peripheral region.
According to an embodiment of the present invention, the forming of the plate at the same time as that of the wall includes the steps of forming a trench peripheral to the substrate portion corresponding to the component, to partially expose the insulator; forming an insulating layer on the trench walls; opening the protection layer to partially expose the peripheral region; depositing a conductive material simultaneously in the trench and around it on the protection layer so that its surface is substantially planar; and etching the conductive material to form the plate in contact with the peripheral region and, in the trench, the lateral wall.
According to an embodiment of the present invention, the step of etching the conductive material is performed to form, at the same time as the plate in contact with the peripheral region, the additional plate.
According to an embodiment of the present invention, the conductive material is a doped semiconductor of the first conductivity type.
According to an embodiment of the present invention, the substrate includes a buried layer of the first conductivity type resting on the insulator, the peripheral region being put in contact with the buried layer by a vertical region.
According to an embodiment of the present invention, the method further includes, between the steps of forming the tre
Morris James H.
Ngo Ngan V.
STMicroelectronics A.A.
Wolf Greenfield & Sacks P.C.
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