High voltage NMOS pass gate for integrated circuit with high vol

Details High voltage NMOS pass gate for integrated circuit with high vol High voltage NMOS pass gate for integrated circuit with high vol

1997-10-06

1998-12-22

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 1300

Patent

active

058525769

ABSTRACT:
Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

REFERENCES:
patent: 5039882 (1991-08-01), Arawaka
patent: 5315188 (1994-05-01), Lee
patent: 5333122 (1994-07-01), Ninomiya

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