Static information storage and retrieval – Read/write circuit – Erase
Patent
1993-01-05
1994-08-02
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Erase
3072966, 365900, G11C 700
Patent
active
053352009
ABSTRACT:
An improved negative charge pump system for erasing a memory array in a memory which has a supply voltage and a negative charge pump. The negative charge pump system includes (a) a device for selecting a memory array to be erased; (b) a device for switching on the supply voltage Vnn for the charge pump; (c) a device for pumping the supply voltage Vnn with the charge pump to produce a pumped negative voltage; (d) a device for erasing the selected array with the pumped negative voltage; (e) a device for stopping the pumping; and (f) a device for providing a discharge path for voltages trapped in the charge pump.
REFERENCES:
patent: 4752699 (1988-06-01), Cranford et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5168174 (1992-12-01), Naso et al.
patent: 5235544 (1993-08-01), Caywood
John F. Dickson, "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique", Jun., 1976.
Witters et al., "Analysis and Modeling of On-Chip High-Voltage Generator Circuits for Use in EEPROM Circuits", Oct., 1989.
Coffman Tim M.
Lin Sung-Wei
Donaldson Richard L.
Headley Tim
Heiting Leo N.
LaRoche Eugene R.
Nguyen Tan
LandOfFree
High voltage negative charge pump with low voltage CMOS transist does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High voltage negative charge pump with low voltage CMOS transist, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High voltage negative charge pump with low voltage CMOS transist will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-69664