High-voltage N-channel MOS transistor and associated manufacturi

Details High-voltage N-channel MOS transistor and associated manufacturi High-voltage N-channel MOS transistor and associated manufacturi

1996-02-27

1998-12-15

Nelms, David

Static information storage and retrieval

Systems using particular element

Semiconductive

365156, 257371, 257336, 257339, G11C 1134

Patent

active

058503609

ABSTRACT:
A CMOS device and process are disclosed in which two types of N-channel MOS transistors are provided, one being formed in a P-well and one being formed outside the P-well where the relatively low doping concentration of P-type substrate serves as a channel defining region. This second type N-channel transistor an support higher junction voltages due to the lower p-type doping concentration than is possible for the first type N-channel transistor formed in the higher doping concentration P-well. A mask is provided to prevent boron doping in the substrate at the site of the high voltage transistor during the implantation step which defines the P-well.

REFERENCES:
patent: 4697332 (1987-10-01), Joy et al.
patent: 5321287 (1994-06-01), Uemura et al.
patent: 5512769 (1996-04-01), Yamamoto
patent: 5568418 (1996-10-01), Crisenza et al.

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