High voltage MOS transistor with gate extension

Details High voltage MOS transistor with gate extension High voltage MOS transistor with gate extension

2004-06-28

2008-05-20

Doan, Theresa T (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C257S331000, C257S340000

Reexamination Certificate

active

07374982

ABSTRACT:
A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled togther and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers. The high voltage MOS transistor of the present invention may be fabricated without additional processing steps in BiCMOS and CMOS processes that use dual polysilicon layers and a dielectric layer that are used to form capacitors.

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