Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-19
2004-08-31
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257S408000, C257S409000
Reexamination Certificate
active
06784490
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an MOS transistor with an increased breakdown voltage (which will be herein called a “high-voltage MOS transistor”) and a method for fabricating the transistor.
Various structures have been specially designed for a high-voltage MOS transistor. Among other things, a LOCOS off-set structure is particularly effectively applicable to an MOS transistor, of which the gate, source and drain all have to have an increased breakdown voltage (e.g., as in a liquid crystal display driver). In the LOCOS offset structure, a relatively thick field oxide film (typically, a locally oxidized silicon (LOCOS) film) is formed around the edges of the gate electrode of an MOS transistor or between the gate electrode and source/drain regions thereof.
The LOCOS offset structure includes offset regions and well offset regions. The offset regions together form a lightly-doped layer under the LOCOS regions that are located around the edges of a gate electrode. These offset regions are provided mainly to prevent the intensity of an electric field from increasing too much at the pn junction between the drain region and a region under the gate electrode. The off-set regions are of the same conductivity type as the source/drain regions but doped more lightly than the source/drain regions. The well offset regions also form a lightly-doped layer under the source/drain regions, but are located deeper than the offset regions. These well offset regions are provided mainly to prevent the intensity of an electric field from increasing too much in the pn junction between the drain region and a well or a substrate region of the opposite conductivity type under the drain region. The well offset regions are also of the same conductivity type as the source/drain regions and the offset regions but are doped even more lightly than the offset regions. That is to say, the source/drain, offset and well offset regions are all of a conductivity type, but their dopant concentrations decrease in this order. Specifically, the source/drain regions have the highest dopant concentration, the offset regions have the next highest and the well offset regions the lowest.
Hereinafter, a known high-voltage MOS transistor with the LOCOS offset structure will be described with reference to
FIGS. 11 and 12
.
FIGS. 11 and 12
are respectively a cross-sectional view and a plan view illustrating the known high-voltage MOS transistor. As shown in
FIGS. 11 and 12
, the high-voltage transistor is normally formed along with a transistor with a low breakdown voltage (which will be herein called a “low-voltage transistor”) on the same chip. In the example illustrated in
FIGS. 11 and 12
, the high- and low-voltage transistors a and b are implemented as an n-channel MOS transistor (NMOS) and a p-channel MOS transistor (PMOS), respectively.
First, the structure of the high-voltage transistor a will be described. A p-well
2
is defined for the high-voltage NMOS a inside a p-type substrate
1
and a gate electrode
8
is formed over the p-well
2
with a gate oxide film
7
interposed therebetween. LOCOS regions
6
are formed around the edges of the gate electrode
8
and between the gate electrode
8
and source/drain regions
9
s
and
9
d
to electrically isolate the gate electrode
8
from the source/drain regions
9
s
and
9
d
on the surface of the substrate
1
. Source/drain offset regions
4
s
and
4
d
are provided under the LOCOS regions
6
around the edges of the gate electrode
8
. And source/drain well offset regions
3
s
and
3
d
are further provided under the source/drain regions
9
s
and
9
d
. The source offset and well offset regions
4
s
and
3
s
are not always needed because, normally, the intensity of an electric field should not increase so much on the source side according to ordinary specifications. However, a transistor device is usually formed symmetrically to have source/drain regions of the same length and with the same dopant concentration. This is because the source/drain regions should not be fixed but are preferably used interchangeably. That is to say, the lengths Ls and Ld of the source/drain offset regions
4
s
and
4
d
are preferably equal to each other. In addition, the length
0
d
of a region overlapping between the drain offset and well offset regions
4
d
and
3
d
is also equal to the length
0
s
of a region overlapping between the source offset and well offset regions
4
s
and
3
s
. In this structure, the gate, source and drain regions of the NMOS a are electrically isolated from a channel stopper
10
, which is a doped layer for creating a potential in the p-well
2
, by n- and p-type isolating regions
4
and
5
and LOCOS regions
6
.
Next, the structure of the low-voltage transistor b will be described. An n-well
3
is defined for the low-voltage PMOS b inside the p-well
2
. Another gate electrode
8
is formed over the n-well
3
with the gate oxide film
7
interposed therebetween, and source/drain regions
11
s
and
11
d
are defined on the left- and right-hand sides of the gate electrode
8
. In this structure, the gate, source and drain regions of the PMOS b are electrically isolated from a channel stopper
12
, which is a doped layer for creating a potential in the n-well
3
, by the n- and p-type isolating regions
4
and
5
and the LOCOS regions
6
.
Hereinafter, a method for fabricating the known high-voltage MOS transistor with the LOCOS offset structure will be described with reference to FIGS.
13
(
a
) through
13
(
d
).
First, as shown in FIG.
13
(
a
), the p-well
2
is defined in the surface region of the p-type substrate
1
by photolithography, ion implantation and annealing processes. Next, as shown in FIG.
13
(
b
), the n-well
3
and the source/drain well offset regions
3
s
and
3
d
are defined in respective surface regions of the p-well
2
by photolithography, ion implantation and annealing processes. Subsequently, as shown in FIG.
13
(
c
), the n- and p-type isolating regions
4
and
5
and the source/drain offset regions
4
s
and
4
d
are formed in the upper parts of the p-well
2
by photolithography and ion implantation processes. Then, the LOCOS regions
6
are formed to cover these regions. Thereafter, as shown in FIG.
13
(
d
), the gate oxide film
7
and the gate electrodes
8
are formed on the surface of the substrate
1
. Finally, the source/drain regions
9
s
and
9
d
and
11
s
and
11
d
and the channel stoppers
10
and
12
are formed by photolithography, ion implantation and annealing processes. In this manner, the high- and low-voltage MOS transistors a and b are formed on the same chip.
Next, it will be described how the known high-voltage MOS transistor with the LOCOS offset structure operates. When a high voltage is applied to the gate electrode
8
and the drain region
9
d
, the high-voltage NMOS a turns ON. Then, not only the drain region
9
d
but also the drain offset and well offset regions
4
d
and
3
d
, which are lightly-doped layers of the same conductivity type as the drain region
9
d
, are depleted. Thus, it is possible to prevent the intensity of an electric field from increasing too much locally around the drain region
9
d
. As a result, the breakdown voltage of the NMOS a can be increased sufficiently.
In the known structure, however, a substrate potential VW easily exceeds a source potential VS. More exactly, the substrate potential VW minus the forward biased breakdown voltage of silicon often exceeds the source potential VS. Accordingly, a breakdown voltage, causing avalanche breakdown of a transistor called “sustaining breakdowns” (which will be herein called a “sustaining breakdown voltage”), is adversely low.
Hereinafter, it will be described with reference to FIGS.
14
(
a
) and
14
(
b
) how and when the sustaining breakdown occurs in the known high-voltage MOS transistor with the LOCOS offset structure. In the following description, the sustaining breakdown of the NMOS a will be explained for illustrative purposes. FIGS.
14
(
a
) and
14
(
b
)
Inoue Haruko
Kitamura Yuichi
Loke Steven
Nixon & Peabody LLP
Studebaker Donald R.
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