High-voltage level tolerant transistor circuit

Details High-voltage level tolerant transistor circuit High-voltage level tolerant transistor circuit

2000-05-15

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000, C326S087000

Reexamination Certificate

active

06320414

ABSTRACT:

The invention relates to a high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor operatively connecting to a high-voltage level node and a second transistor operatively connecting to a low-voltage level node, wherein said first transistor connects to a biasing circuit providing a variable biasing level.
In field effect transistors, for example, high electrical fields across the gate oxide leads to oxide degradation and eventually breakdown. Hot channel electron injection, due to over-voltages, also yields gate oxide degradation. In present field effect transistors, electrical oxide fields up to 5.5 MV/cm are acceptable. Junction breakdown poses in general no serious problem for voltages at twice the nominal supply voltage of a transistor. The main cause of transistor degradation is, however, formed by hot-electron injection providing an accumulated degradation at voltages above the nominal supply voltage.
High-voltage level tolerant transistor circuits are, for example, used as Input/Output (I/O)-buffer circuits between electronic circuitry such as I/O cells, operating at different supply voltages. In ordinary I/O cells, the output voltage swing is equal or lower than the nominal supply voltage allowed for the semiconductor process in which the circuit is realised. To increase the tolerable voltage swing at the I/O pad without running into lifetime problems of the transistors from too high electrical fields across the transistor terminals, the operating voltages across the terminals of the transistors of the cell have to be limited. This is typically done by using properly biased cascoded transistors, such as disclosed in U.S. Pat. No. 5,825,206.
According to this prior art solution, complex data signal controlled biasing circuitry is used for biasing the cascoded transistors in order to avoid lifetime problems.
It is an object of the invention to provide a simple high-voltage tolerant transistor circuit robust to at least twice the nominal internal supply voltage of the circuit.
To this end, according to the invention, the biasing circuit is arranged for providing a biasing level relative to the voltage level at the high-voltage level node.
The invention is based on the recognition that life-time problems of, for example, the cascoded transistor connecting to the high-voltage level node can be reduced by controlling the biasing level of this transistor in response to the voltage at the high-voltage level node.
Following the invention, the biasing voltage level is decreased if the voltage level at the high-voltage level node is below a first threshold and the biasing voltage level is increased if the voltage level at the high-voltage level node is above a second threshold. The first and second thresholds and the actual biasing voltage levels have to be chosen such that differences between the voltage level at the high-voltage level node and the biasing voltage level do not exceed values of approximately the nominal supply voltage of the transistor circuit.
In an embodiment of the biasing circuit according to the invention, a voltage level shifter operative in response to the voltage level at the high-voltage level node is used to obtain the desired biasing level of the first cascoded transistor.
In a relatively simple embodiment of the high-voltage level tolerant transistor circuit according to the invention, a third transistor is cascoded between the first and second transistor, wherein the first and third transistor having their control electrode connected for biasing by an internal supply voltage of the transistor circuit, and wherein the voltage level shifter comprises at least one fourth transistor operatively connected as a diode for bypassing the first transistor.
The number of diode connected transistors is determined by the maximum tolerable voltage at the high-voltage level node and the maximum junction voltage of the first transistor, such as the drain-gate voltage in case of a field effect transistor.
In order to avoid limitation of the voltage level at the high-voltage level node by the drain-gate voltage of the first transistor, in a further embodiment of the invention, an active control for the biasing voltage at the control electrode of the first transistor is provided in that the biasing circuit comprises a bistable trigger circuit having a biasing terminal for applying a biasing voltage, wherein the trigger circuit is arranged for providing a variable biasing level for biasing the first transistor in response to the voltage level at the high-voltage level node.
In case of a field effect transistor, the bistable trigger circuit according to the invention provides an active control of the drain-gate voltage of the first transistor, dependent on the above-mentioned first and second thresholds.
In an embodiment of the biasing circuit according to the invention, the trigger circuit comprises a fifth and sixth transistor of opposite conductivity type compared to the first transistor, the fifth and sixth transistor having a first channel electrode operatively connected to a control electrode of the first transistor, the fifth transistor having a second channel electrode comprising the biasing terminal, the sixth transistor having a second channel electrode connected to a first channel electrode of the first transistor downstream of said high-voltage level node, and the fifth and sixth transistor having their control electrode operatively connected to the second channel electrode of the sixth and fifth transistor, respectively.
In the case of field effect transistors, the bistable trigger circuit operates such that the gate-source voltage of the first cascode transistor is low for a high-voltage at the high-voltage level node, and the gate-source voltage of the first transistor is high if the voltage at the high-voltage level node is low.
In a preferred embodiment of the transistor circuit according to the invention, the trigger circuit comprises a fifth and sixth transistor of opposite conductivity type compared to the first transistor, the fifth and sixth transistor having a first channel electrode operatively connected to a control electrode of the first transistor, the fifth transistor having a second channel electrode comprising the biasing terminal, the sixth transistor having a second channel electrode connected to a second channel electrode of the first transistor upstream towards the high-voltage level node, and the fifth and sixth transistor having their control electrode operatively connected to the second channel electrode of the sixth and fifth transistor, respectively.
With this preferred embodiment, in the case of field effect transistors, the drain-gate voltage of the first cascode transistor is controlled providing less leakage current.
Advantageously, because of reducing the channel hot-electron injection without increasing the oxide fields, the above bistable trigger biasing circuits are stackable for plural cascoded first transistors, wherein the biasing terminal of a stack is operatively connected to the control electrode of a first transistor of an adjacent stack downstream of the high-voltage level node. In practice, in the case of field effect transistors, with each added cascoded transistor and associated biasing circuit, the tolerable voltage at the high-voltage level node is roughly increased by 1 V.
For applications in which the tolerable voltage provided by a single first transistor and bistable biasing circuit is just (a fraction) too low, an extra cascode stage can be prevented by the expense of the addition of a relatively small level shifter, such as a diode connected transistor, operatively series connected with the second electrode of the sixth transistor.
In the case of stacked first transistors and associated biasing circuits, if the tolerable voltage level is just too low, addition of a further stack can be prevented at the expensive of a yet further voltage level shifter operatively series connected with the biasing supply voltage.
In an embodiment of the tr

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