Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-12-11
2003-11-11
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S068000
Reexamination Certificate
active
06646469
ABSTRACT:
TECHNICAL FIELD
This invention relates to power switches, and more specifically, to an improved technique of providing level shifting required in a floating high side power switch in the half bridge configuration. The invention has specific application in power switches utilizing field effect transistor (FET) devices.
BACKGROUND OF THE INVENTION
A half bridge configuration is utilized in connection with various power switch applications. Such a half bridge configuration typically involves an output signal interposed between two powered FET devices. An example of such prior art arrangement is shown in FIG.
1
.
In operation, the output signal V
HB
may fluctuate from nearly zero volts with respect to ground point
101
, up to nearly 400 volts, depending upon the parameters of the amplifying circuit and input power introduced into the circuit.
In order to properly operate transistor T
1
in its normal operating region, the gate voltage G
1
must be controlled with reference to the output signal V
HB
, not with respect to ground. Therefore, the power voltage F
VDD
should ideally be the equivalent of the voltage V
DD
of
FIG. 1
, except shifted by an amount substantially equal to V
HB
. Additionally, the gateway voltage G
1
for transistor T
1
should be equal to the appropriate voltage to turn on a transistor (e.g., G
2
), shifted up by an amount substantially equal to V
HB
.
The circuitry for shifting the power source F
VDD
is known in the art and not critical to the present invention. Numerous circuits and related arrangements exist for generating such a voltage, and will not be discussed in detail herein. The particular circuitry used to generate the F
VDD
is not critical to the present invention.
In operation, a non-overlapping circuit
105
generates two non-overlapping pulses
106
and
107
. The first pulse
106
is transmitted via a driver
108
to the gate G
2
of a power transistor T
2
. Since the voltage is controlling transistor T
2
must be set with respect to a ground voltage, no level shifting is required.
Gate voltage G
1
controlling transistor T
1
must however, be set with respect to voltage V
HB
. Therefore, the remaining circuitry included within
FIG. 1
is directed largely at voltage shifting the pulse
107
to provide the appropriate gate voltage G
1
adjusted by the dynamically moving signal V
HB
, which may be anywhere between zero and 400 volts.
In order to obtain the appropriate shift, two fixed current sources
112
and
114
are utilized. When the pulse generator
115
is on a rising edge, current source
114
is on and current source
112
is off. On a falling edge, the reverse happens, current source
112
being on and current source
114
being turned off.
In analysis of the remaining circuitry will show that power devices M
1
and M
2
each alternatively generate the required current through resistors M
9
and M
10
at the appropriate time in order to either set or reset, as appropriate, latch
116
. Therefore, upon rising edges latch
116
sets, and upon falling edges the latch resets. This causes the output of driver
117
to generate the appropriate gate voltage required to control transistor T
1
. Notably, since both the driver
117
and latch
116
are referenced to V
HB
, and since the supply voltage F
VDD
is shifted by V
HB
, everything operating with respect to transistor T
1
is with reference to V
HB
.
In summary, the circuitry of
FIG. 1
operates by utilizing two current sources, a first of which induces a current sufficient to turn on a “set” transistor, and a second of which induces a current to turn on a “reset” transistor. By turning the appropriate current sources on or off at the appropriate times, a latch
116
is set or reset, and a driver
117
is controlled at a voltage that is relative not to ground but to a variable level signal V
hb
. This scenario appropriately drives the transistor T
1
.
A problem with the circuit of
FIG. 1
is that it is lossy. The devices M
1
and M
2
and current sources
112
and
114
represent lossy devices, which waste relatively large amounts of power, particularly at high frequencies. Additionally, the current sources
112
and
114
are subject to the normal failure that is inherent in such active devices.
Therefore, it is desirable to provide a high power switching arrangement that can be utilized in a half bridge configuration while eliminating the high losses associated with active devices.
It is also desirable that such a circuit has a low manufacturing cost, and that it be more reliable than is presently achievable.
SUMMARY OF THE INVENTION
The above and other problems of the prior art are overcome in accordance with the present invention. Active devices utilized to effectuate the currents required to switch a latch are replaced with passive devices and small drivers. The drivers and passive devices have far less conduction losses than the active high voltage switches and current sources previously utilized.
In one preferred embodiment, the passive devices are capacitors, and the current is induced by a sudden change in voltage induced at one terminal of the capacitor. Since the capacitor has very low impedance at high frequencies, the sudden change in voltage induces a current large enough and for long enough to set or reset the latch as appropriate. Therefore, the capacitor, as a passive device, provides the required current required to set and reset a latch, and thus properly drive a transistor, rather than using an active device.
REFERENCES:
patent: 5572156 (1996-11-01), Diazzi et al.
patent: 5742196 (1998-04-01), Fronen et al.
patent: 6353345 (2002-03-01), Yushan et al.
Biren Steven R.
Le Don
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