High voltage level shifter for driving an output stage

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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Details

C327S112000, C327S333000, C326S068000

Reexamination Certificate

active

06236244

ABSTRACT:

TECHNICAL FIELD
This invention relates to an electronic level shifter circuit for driving a high-voltage output power stage.
More particularly, the invention relates to an electronic level shifter circuit for driving a high-voltage output stage, said stage comprising a complementary pair of transistors connected between first and second supply voltage references, and including at least one PMOS pull-up transistor connected in series to an NMOS pull-down transistor.
BACKGROUND OF THE INVENTION
As is well known, a final output stage of a generic electronic circuit basically includes a drive portion intended for powering a load whichever. Thus, the output stage should be capable of draining or taking up current from the load, according to necessity and the type of application involved.
Countless configurations have been proposed in the prior art for the output stage.
FIG. 1
attached hereto shows schematically one of the commonest of such output stage configurations.
The stage shown in
FIG. 1
comprises a complementary pair of MOS transistors connected in series with each other, between a first voltage reference Vdd and a second voltage reference Vss, wherein the latter may either be a negative supply or a ground.
Complementary pairs of MOS transistors are those more often employed in output stages on account of the definite advantages that they afford in the respect of control logics; however, the considerations made herein below would also apply to output stage configurations incorporating bipolar transistors or any other pairs of MOS transistors.
The first transistor M
7
in the complementary pair is a pull-down transistor of either the NMOS or the DMOS type, and has its body terminal connected to the source terminal.
The second transistor M
6
in the complementary pair is a pull-up transistor of the thin oxide PMOS type, and has its body terminal connected to the source terminal.
The transistors M
6
and M
7
are connected to each other through their respective drain terminals, which terminals coincide with an output node OUT. An electric load, not shown, is connected between the output node OUT and ground.
The electric load is driven alternately by the PMOS transistor M
6
or the NMOS transistor M
7
, according to whether the operation phase is one of sourcing or of sinking.
Respective driving stages have their respective outputs connected to the gate terminals of the transistors M
6
and M
7
. Only the driving stage of the PMOS transistor M
6
is shown in FIG.
1
.
FIG. 2
shows a second example of an output stage incorporating a pair of NMOS and PMOS transistors M
15
and M
23
. These transistors are again connected together at the output node OUT, and a driving stage of greater complexity than in the previous example of
FIG. 1
is provided for the PMOS transistor M
23
.
FIG. 3
shows schematically a further embodiment wherein all the PMOS transistors shown in
FIG. 2
are replaced with similar thick oxide PMOS power transistors.
SUMMARY OF THE INVENTION
For many applications, output stages which can operate in both low driving voltage and high driving voltage conditions would be desirable.
However, the prior art provides no solutions which can efficiently fill the demand in terms of performance as well as of reduced occupation of circuit area.
An embodiment of this invention provides an output stage and associated level shifting driver circuit with such respective functional and structural features as to be usable in low- and high-voltage applications and to have reduced circuit area requirements.
The embodiment provides an output stage which incorporates both a thin gate oxide PMOS transistor and a thick field oxide PMOS transistor, and of having both transistors driven from the same level shifting driver circuit.
Features and advantages of the this invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.


REFERENCES:
patent: 5124579 (1992-06-01), Naghshineh
patent: 5128555 (1992-07-01), Millman
patent: 5440258 (1995-08-01), Galbi et al.
patent: 5760621 (1998-06-01), Keeth
patent: 5896044 (1999-04-01), Walden
patent: 6028574 (2000-02-01), Bancal
patent: 6087852 (2000-07-01), Briggs et al.
patent: 0238358 (1987-09-01), None
“New PMOS Pull-Up Circuit for Dual-Power Supply”IBM Technical Disclosure Bulletin, IBM Corporation, Armonk, New York, Jun. 1993, pp. 183-185.

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