Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1997-03-26
1998-12-22
Santamauro, Jon
Electronic digital logic circuitry
Interface
Logic level shifting
326 81, 326102, 257408, H03K 190185
Patent
active
058523669
ABSTRACT:
In order to solve problems of a conventional level shift circuit which is difficult to use since a bias voltage is needed and where a number of P-channel MOSFETs is large and an area thereof is large, a level shift circuit comprises N-channel MOSFETs N1, N2 and N3 gates of which are respectively connected to input terminals 1, 2 and 3 and sources of which are commonly connected to a low potential side power source terminal, and P-channel MOSFETs P1, P2 and P3 sources of which are connected commonly to a high potential side power source terminal and drains of which are connected respectively to drains of the N-channel MOSFETs N1, N2 and N3. The P-channel MOSFETs P1 and P2 are provided with drain intermediate taps T1 and T2, the gate of the P-type MOSFET P1 is connected to the drain intermediate tap T2 of the P-channel MOSFET P2 and the gate of the P-channel MOSFET P2 is connected to the drain intermediate tap T1 of the P-channel MOSFET P1. The P-channel MOSFET P3 is a transistor for outputting and the gate thereof is connected to the drain intermediate tap T2 of the P-channel MOSFET P2.
REFERENCES:
patent: 5306656 (1994-04-01), Williams et al.
NEC Corporation
Santamauro Jon
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