High voltage LDMOS transistor having an isolated structure

Details High voltage LDMOS transistor having an isolated structure High voltage LDMOS transistor having an isolated structure

2006-02-07

2006-02-07

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S213000, C257S288000, C257S327000

Reexamination Certificate

active

06995428

ABSTRACT:
A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.

REFERENCES:
patent: 6448625 (2002-09-01), Hossain et al.
Tsui et al., “Integration of power LDMOS into low-voltage 0.5 μm BiCMOS technology,” International Electron Devices Meeting 1992, Technical Digest, p. 27-30.

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