Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-17
2002-08-27
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S339000, C257S327000, C257S328000, C257S343000
Reexamination Certificate
active
06441432
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a high voltage lateral semiconductor device that is formed on an SOI (Silicon-On-Insulator) substrate fabricated by a wafer bonding method.
BACKGROUND OF THE INVENTION
While the development of isolation techniques such as junction isolation and dielectric isolation in recent years, high voltage power ICs have been extensively developed wherein high voltage devices, such as diodes, insulated gate bipolar transistors (hereinafter referred to as “IGBT”), and MOSFET, which have lateral structures, are integrated with a drive circuit, control circuit and a protection circuit for the devices on a single silicon substrate. In particular, the dielectric isolation technique that employs an SOI substrate fabricated by a wafer bonding method along with a trench-formation technique enables integration of a plurality of high voltage bipolar devices (such as bipolar transistors and IBGT), thus permitting significantly extended applications of high voltage power ICs. For example, this technique permits formation of a totem pole circuit using IGBTs in a single chip, and the use of IGBTs in an integrated circuit, such as an IC for driving a display, that is capable of generating a plurality of outputs.
In the development of high voltage power IC, it is highly desired to improve the performance of high voltage output devices for directly driving a load, and also improve the characteristics of an output circuit including the output devices. High voltage MOSFETs are essential devices in the configuration of the output circuit. Even where the MOSFET is not used as an output device, therefore, the output characteristics of high voltage power IC are greatly influenced by the performance of the high voltage MOSFETs, as well as that of the output devices for driving a load.
FIG. 5
illustrates an output circuit of a high voltage power IC by way of example. This circuit is incorporated in a high voltage power IC adapted for driving a flat panel display. In
FIG. 5
, VL, V
in
1
, V
in
2
, Vss, VH, and V
out
represent respective terminals of the circuit, more specifically, VL is denotes a high-potential terminal of a low-voltage power supply, V
in
1
, V
in
2
denote input terminals of a shift register
21
. Vss denote a common low-potential terminal (ground terminal) of the low-voltage power supply and high-voltage power supply, VH is a high-potential terminal of the high-voltage power supply, and V
out
denotes an output terminal. The output circuit includes output devices N
1
and N
2
that consist of IGBTs, diodes D
1
, D
2
, p channel MOSFET P
1
, n channel MOSFET N
3
, Zener diode ZD, and resistances R
1
, R
2
. The output circuit further includes a buffer
19
, a level shifter
20
and a shift register
21
.
The operation of the above-described circuit will be now explained. Signals for driving the output devices N
1
, N
2
are applied from V
in
1
and V
in
2
to the shift register
21
, and the signal for driving the device N
2
is fed to the gage of the p channel MOSFET P
1
via the level shifter
20
. As a result, the p channel MOSFET P
1
is turned on, and the output device N
2
is turned on. At the same time, an OFF signal is applied to the output device N
1
via the buffer
19
so that the device N
1
is turned off. The p channel MOSFET P
1
is then turned off so that the n channel MOSFET N
3
is turned on, whereby the output device N
2
is turned off while the output device N
1
is turned on. In this circuit, the devices N
1
, N
2
, which are IGBTs, serve as output devices for driving a load, and both of the devices N
3
, P
1
consist of lateral MOSFET having a high breakdown voltage. Although the devices N
3
, P
1
do not serve to directly drive the load, they play an important role in driving the output devices N
1
, N
2
. If the characteristics, such as a breakdown characteristic, of these devices N
3
, P
1
are unsatisfactory or poor, the high voltage power IC cannot provide desired output characteristics even if the output devices N
1
N
2
themselves exhibit good characteristics. Thus, it is important in the high voltage power IC to ensure sufficiently high breakdown voltage of the lateral MOSFETs N
3
, P
1
of the output circuit, while assuring good characteristics of the output devices.
FIG. 6
is a cross-sectional view showing a principal part of a lateral MOSFET formed on an SOI substrate. The MOSFET of
FIG. 6
includes an n type semiconductor substrate
40
as a first conductivity type semiconductor substrate, and is adapted to form an n type channel therein.
To form the lateral MOSFET, a bonding oxide film
2
is formed on a support substrate
1
in the form of an n type or p type semiconductor substrate, and the n type semiconductor substrate
40
is bonded onto the oxide film
2
, and then polished, to thus provide an SOI substrate
70
. Thereafter, a p well region
4
, a p
+
contact region
5
, and an n
+
source region
6
are formed in a surface layer of the n type semiconductor substrate
40
. An n buffer region
14
is formed in the semiconductor substrate
40
apart from the p well region
4
, and an n
+
drain region
11
is formed in a surface layer of the n buffer region
14
. The n type semiconductor substrate
40
that is interposed between the p well region
4
and the n buffer region
14
provides an n drift region
3
. A gate electrode
8
is formed on a gate oxide film
7
over the p well region
4
. A source electrode
9
is formed in contact with the n
+
source region
6
and the p
+
contact region
5
, and a drain electrode
12
is formed on the n
+
drain region
11
. The source electrode
9
, gate electrode
8
, and the drain electrode
12
are connected to a source terminal S, a gate terminal G, and a drain terminal D, respectively.
In the MOSFET having a lateral structure as shown in the cross-sectional view of
FIG. 7
, the source electrode
9
, gate electrode
8
and the drain electrode
12
are all formed on the same surface of the semiconductor substrate. The support substrate
1
is normally fixed at the ground potential, namely, the support substrate
1
is normally grounded. The device is insulated from the support substrate
1
by the bonding oxide film
2
interposed therebetween. In operation, electrons that constitute current are injected from the n
+
source region
6
into the n
+
drift region
3
through an n channel, and then flow into the n
+
drain region
11
through the n buffer region
14
.
FIG. 7
is a potential distribution diagram showing the potential distribution inside the device when a high voltage is applied to the lateral MOSFET on the SOI substrate. The breakdown voltage of the device used in this simulation is 320 V.
FIG. 7
shows the results of the potential distribution obtained in a simulation test in which the n
+
source region
6
, p
+
contact region
5
and gate electrode
8
are grounded, and a voltage of 320 V is applied to the drain region
11
. In
FIG. 7
, equipotential lines
16
are drawn for every 10 V, namely, each interval between adjacent equipotential lines represents a 10 V potential difference. In this example, the bonding oxide film
2
of the SOI substrate has a thickness of 2 &mgr;m, which is 1 &mgr;m thicker than that of the device of a preferred embodiment that will be described later. The support substrate is not illustrated in FIG.
7
.
It will be understood from
FIG. 7
that the potential as represented by the equipotential lines
16
becomes higher as the location of measurement gets closer to the n
+
drain region
11
, and that an increased number of equipotential lines
16
are present on the side of the n
+
drain region
11
. Namely, when a high voltage is applied to the lateral MOSFET formed on the SOI substrate, the voltage within the device is maintained on the side of the n
+
drain region
11
. With the n buffer region
14
provided in this example, a high density of equipotential lines
16
are present at around the n buffer region
14
.
FIG. 8
shows
Fuji Electric & Co., Ltd.
Lee Eddie
Nguyen Joseph
Rossi & Associates
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